1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * $Id$
32 *
33 * Description: Perfect switch, of course it is perfect and no latency or what
34 * so ever. Every cycle it is woke up and perform all the
35 * necessary routings that must be done. Note, this switch also
36 * has number of input ports/output ports and has a routing table
37 * as well.
38 *
39 */
40
41#ifndef PerfectSwitch_H
42#define PerfectSwitch_H
43
| 1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * $Id$
32 *
33 * Description: Perfect switch, of course it is perfect and no latency or what
34 * so ever. Every cycle it is woke up and perform all the
35 * necessary routings that must be done. Note, this switch also
36 * has number of input ports/output ports and has a routing table
37 * as well.
38 *
39 */
40
41#ifndef PerfectSwitch_H
42#define PerfectSwitch_H
43
|
| 44#include <iostream>
45
|
44#include "mem/ruby/common/Global.hh"
45#include "mem/gems_common/Vector.hh"
46#include "mem/ruby/common/Consumer.hh"
47#include "mem/ruby/system/NodeID.hh"
48
49class MessageBuffer;
50class NetDest;
51class SimpleNetwork;
52
53class LinkOrder {
54public:
55 int m_link;
56 int m_value;
57};
58
59class PerfectSwitch : public Consumer {
60public:
61 // Constructors
62
63 // constructor specifying the number of ports
64 PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr);
65 void addInPort(const Vector<MessageBuffer*>& in);
66 void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry);
67 void clearRoutingTables();
68 void clearBuffers();
69 void reconfigureOutPort(const NetDest& routing_table_entry);
70 int getInLinks() const { return m_in.size(); }
71 int getOutLinks() const { return m_out.size(); }
72
73 // Destructor
74 ~PerfectSwitch();
75
76 // Public Methods
77 void wakeup();
78
| 46#include "mem/ruby/common/Global.hh"
47#include "mem/gems_common/Vector.hh"
48#include "mem/ruby/common/Consumer.hh"
49#include "mem/ruby/system/NodeID.hh"
50
51class MessageBuffer;
52class NetDest;
53class SimpleNetwork;
54
55class LinkOrder {
56public:
57 int m_link;
58 int m_value;
59};
60
61class PerfectSwitch : public Consumer {
62public:
63 // Constructors
64
65 // constructor specifying the number of ports
66 PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr);
67 void addInPort(const Vector<MessageBuffer*>& in);
68 void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry);
69 void clearRoutingTables();
70 void clearBuffers();
71 void reconfigureOutPort(const NetDest& routing_table_entry);
72 int getInLinks() const { return m_in.size(); }
73 int getOutLinks() const { return m_out.size(); }
74
75 // Destructor
76 ~PerfectSwitch();
77
78 // Public Methods
79 void wakeup();
80
|
79 void printStats(ostream& out) const;
| 81 void printStats(std::ostream& out) const;
|
80 void clearStats();
| 82 void clearStats();
|
81 void printConfig(ostream& out) const;
| 83 void printConfig(std::ostream& out) const;
|
82
| 84
|
83 void print(ostream& out) const;
| 85 void print(std::ostream& out) const;
|
84private:
85
86 // Private copy constructor and assignment operator
87 PerfectSwitch(const PerfectSwitch& obj);
88 PerfectSwitch& operator=(const PerfectSwitch& obj);
89
90 // Data Members (m_ prefix)
91 SwitchID m_switch_id;
92
93 // vector of queues from the components
94 Vector<Vector<MessageBuffer*> > m_in;
95 Vector<Vector<MessageBuffer*> > m_out;
96 Vector<NetDest> m_routing_table;
97 Vector<LinkOrder> m_link_order;
98 int m_virtual_networks;
99 int m_round_robin_start;
100 int m_wakeups_wo_switch;
101 SimpleNetwork* m_network_ptr;
102};
103
104// Output operator declaration
| 86private:
87
88 // Private copy constructor and assignment operator
89 PerfectSwitch(const PerfectSwitch& obj);
90 PerfectSwitch& operator=(const PerfectSwitch& obj);
91
92 // Data Members (m_ prefix)
93 SwitchID m_switch_id;
94
95 // vector of queues from the components
96 Vector<Vector<MessageBuffer*> > m_in;
97 Vector<Vector<MessageBuffer*> > m_out;
98 Vector<NetDest> m_routing_table;
99 Vector<LinkOrder> m_link_order;
100 int m_virtual_networks;
101 int m_round_robin_start;
102 int m_wakeups_wo_switch;
103 SimpleNetwork* m_network_ptr;
104};
105
106// Output operator declaration
|
105ostream& operator<<(ostream& out, const PerfectSwitch& obj);
| 107std::ostream& operator<<(std::ostream& out, const PerfectSwitch& obj);
|
106
107// ******************* Definitions *******************
108
109// Output operator definition
110extern inline
| 108
109// ******************* Definitions *******************
110
111// Output operator definition
112extern inline
|
111ostream& operator<<(ostream& out, const PerfectSwitch& obj)
| 113std::ostream& operator<<(std::ostream& out, const PerfectSwitch& obj)
|
112{
113 obj.print(out);
| 114{
115 obj.print(out);
|
114 out << flush;
| 116 out << std::flush;
|
115 return out;
116}
117
118#endif //PerfectSwitch_H
| 117 return out;
118}
119
120#endif //PerfectSwitch_H
|