request.hh (7705:fd65f85fcc0c) request.hh (7708:956ac83b0a58)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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69 static const FlagsType ALTMODE = 0x00000800;
70 /** The request is to an uncacheable address. */
71 static const FlagsType UNCACHEABLE = 0x00001000;
72 /** This request is to a memory mapped register. */
73 static const FlagsType MMAPED_IPR = 0x00002000;
74 /** This request is a clear exclusive. */
75 static const FlagsType CLEAR_LL = 0x00004000;
76
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 60 unchanged lines hidden (view full) ---

69 static const FlagsType ALTMODE = 0x00000800;
70 /** The request is to an uncacheable address. */
71 static const FlagsType UNCACHEABLE = 0x00001000;
72 /** This request is to a memory mapped register. */
73 static const FlagsType MMAPED_IPR = 0x00002000;
74 /** This request is a clear exclusive. */
75 static const FlagsType CLEAR_LL = 0x00004000;
76
77 /** The request should ignore unaligned access faults */
78 static const FlagsType NO_ALIGN_FAULT = 0x00020000;
79 /** The request should ignore unaligned access faults */
80 static const FlagsType NO_HALF_WORD_ALIGN_FAULT = 0x00040000;
81 /** The request should not cause a memory access. */
82 static const FlagsType NO_ACCESS = 0x00080000;
83 /** This request will lock or unlock the accessed memory. When used with
84 * a load, the access locks the particular chunk of memory. When used
85 * with a store, it unlocks. The rule is that locked accesses have to be
86 * made up of a locked load, some operation on the data, and then a locked
87 * store.
88 */

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454 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
455 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
456 bool isLLSC() const { return _flags.isSet(LLSC); }
457 bool isLocked() const { return _flags.isSet(LOCKED); }
458 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
459 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
460 bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
461 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
77 /** The request should not cause a memory access. */
78 static const FlagsType NO_ACCESS = 0x00080000;
79 /** This request will lock or unlock the accessed memory. When used with
80 * a load, the access locks the particular chunk of memory. When used
81 * with a store, it unlocks. The rule is that locked accesses have to be
82 * made up of a locked load, some operation on the data, and then a locked
83 * store.
84 */

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450 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
451 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
452 bool isLLSC() const { return _flags.isSet(LLSC); }
453 bool isLocked() const { return _flags.isSet(LOCKED); }
454 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
455 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
456 bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
457 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
462
463 bool
464 isMisaligned() const
465 {
466 if (_flags.isSet(NO_ALIGN_FAULT))
467 return false;
468
469 if ((_vaddr & 0x1))
470 return true;
471
472 if (_flags.isSet(NO_HALF_WORD_ALIGN_FAULT))
473 return false;
474
475 if ((_vaddr & 0x2))
476 return true;
477
478 return false;
479 }
480};
481
482#endif // __MEM_REQUEST_HH__
458};
459
460#endif // __MEM_REQUEST_HH__