request.hh (6899:f8057af86bf7) request.hh (7612:917946898102)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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66 /** The request is an ALPHA VPTE pal access (hw_ld). */
67 static const FlagsType VPTE = 0x00000400;
68 /** Use the alternate mode bits in ALPHA. */
69 static const FlagsType ALTMODE = 0x00000800;
70 /** The request is to an uncacheable address. */
71 static const FlagsType UNCACHEABLE = 0x00001000;
72 /** This request is to a memory mapped register. */
73 static const FlagsType MMAPED_IPR = 0x00002000;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 57 unchanged lines hidden (view full) ---

66 /** The request is an ALPHA VPTE pal access (hw_ld). */
67 static const FlagsType VPTE = 0x00000400;
68 /** Use the alternate mode bits in ALPHA. */
69 static const FlagsType ALTMODE = 0x00000800;
70 /** The request is to an uncacheable address. */
71 static const FlagsType UNCACHEABLE = 0x00001000;
72 /** This request is to a memory mapped register. */
73 static const FlagsType MMAPED_IPR = 0x00002000;
74 /** This request is a clear exclusive. */
75 static const FlagsType CLREX = 0x00004000;
74
75 /** The request should ignore unaligned access faults */
76 static const FlagsType NO_ALIGN_FAULT = 0x00020000;
77 /** The request should ignore unaligned access faults */
78 static const FlagsType NO_HALF_WORD_ALIGN_FAULT = 0x00040000;
79 /** The request should not cause a memory access. */
80 static const FlagsType NO_ACCESS = 0x00080000;
81 /** This request will lock or unlock the accessed memory. When used with

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451 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
452 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
453 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
454 bool isLLSC() const { return _flags.isSet(LLSC); }
455 bool isLocked() const { return _flags.isSet(LOCKED); }
456 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
457 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
458 bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
76
77 /** The request should ignore unaligned access faults */
78 static const FlagsType NO_ALIGN_FAULT = 0x00020000;
79 /** The request should ignore unaligned access faults */
80 static const FlagsType NO_HALF_WORD_ALIGN_FAULT = 0x00040000;
81 /** The request should not cause a memory access. */
82 static const FlagsType NO_ACCESS = 0x00080000;
83 /** This request will lock or unlock the accessed memory. When used with

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453 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
454 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
455 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
456 bool isLLSC() const { return _flags.isSet(LLSC); }
457 bool isLocked() const { return _flags.isSet(LOCKED); }
458 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
459 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
460 bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
461 bool isClrex() const { return _flags.isSet(CLREX); }
459
460 bool
461 isMisaligned() const
462 {
463 if (_flags.isSet(NO_ALIGN_FAULT))
464 return false;
465
466 if ((_vaddr & 0x1))

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463 bool
464 isMisaligned() const
465 {
466 if (_flags.isSet(NO_ALIGN_FAULT))
467 return false;
468
469 if ((_vaddr & 0x1))

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