| request.hh (5466:a1981d557252) | request.hh (5543:3af77710f397) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 39 unchanged lines hidden (view full) --- 48class Request; 49 50typedef Request* RequestPtr; 51 52 53/** ASI information for this request if it exsits. */ 54const uint32_t ASI_BITS = 0x000FF; 55/** The request is a Load locked/store conditional. */ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 39 unchanged lines hidden (view full) --- 48class Request; 49 50typedef Request* RequestPtr; 51 52 53/** ASI information for this request if it exsits. */ 54const uint32_t ASI_BITS = 0x000FF; 55/** The request is a Load locked/store conditional. */ |
| 56const uint32_t LOCKED = 0x00100; | 56const uint32_t LOCKED = 0x00100; |
| 57/** The virtual address is also the physical address. */ | 57/** The virtual address is also the physical address. */ |
| 58const uint32_t PHYSICAL = 0x00200; | 58const uint32_t PHYSICAL = 0x00200; |
| 59/** The request is an ALPHA VPTE pal access (hw_ld). */ | 59/** The request is an ALPHA VPTE pal access (hw_ld). */ |
| 60const uint32_t VPTE = 0x00400; | 60const uint32_t VPTE = 0x00400; |
| 61/** Use the alternate mode bits in ALPHA. */ | 61/** Use the alternate mode bits in ALPHA. */ |
| 62const uint32_t ALTMODE = 0x00800; | 62const uint32_t ALTMODE = 0x00800; |
| 63/** The request is to an uncacheable address. */ | 63/** The request is to an uncacheable address. */ |
| 64const uint32_t UNCACHEABLE = 0x01000; | 64const uint32_t UNCACHEABLE = 0x01000; |
| 65/** The request should not cause a page fault. */ 66const uint32_t NO_FAULT = 0x02000; 67/** The request should be prefetched into the exclusive state. */ | 65/** The request should not cause a page fault. */ 66const uint32_t NO_FAULT = 0x02000; 67/** The request should be prefetched into the exclusive state. */ |
| 68const uint32_t PF_EXCLUSIVE = 0x10000; | 68const uint32_t PF_EXCLUSIVE = 0x10000; |
| 69/** The request should be marked as LRU. */ | 69/** The request should be marked as LRU. */ |
| 70const uint32_t EVICT_NEXT = 0x20000; | 70const uint32_t EVICT_NEXT = 0x20000; |
| 71/** The request should ignore unaligned access faults */ 72const uint32_t NO_ALIGN_FAULT = 0x40000; 73/** The request was an instruction read. */ 74const uint32_t INST_READ = 0x80000; 75/** This request is for a memory swap. */ 76const uint32_t MEM_SWAP = 0x100000; 77const uint32_t MEM_SWAP_COND = 0x200000; 78/** The request should ignore unaligned access faults */ --- 208 unchanged lines hidden --- | 71/** The request should ignore unaligned access faults */ 72const uint32_t NO_ALIGN_FAULT = 0x40000; 73/** The request was an instruction read. */ 74const uint32_t INST_READ = 0x80000; 75/** This request is for a memory swap. */ 76const uint32_t MEM_SWAP = 0x100000; 77const uint32_t MEM_SWAP_COND = 0x200000; 78/** The request should ignore unaligned access faults */ --- 208 unchanged lines hidden --- |