request.hh (4167:ce5d0f62f13b) request.hh (4610:97834b18a8b4)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34 * @file
35 * Declaration of a request, the overall memory request consisting of
36 the parts of the request that are persistent throughout the transaction.
37 */
38
39#ifndef __MEM_REQUEST_HH__
40#define __MEM_REQUEST_HH__
41
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34 * @file
35 * Declaration of a request, the overall memory request consisting of
36 the parts of the request that are persistent throughout the transaction.
37 */
38
39#ifndef __MEM_REQUEST_HH__
40#define __MEM_REQUEST_HH__
41
42#include "base/fast_alloc.hh"
42#include "sim/host.hh"
43#include "sim/core.hh"
44
45#include <cassert>
46
47class Request;
48
49typedef Request* RequestPtr;

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71const uint32_t NO_ALIGN_FAULT = 0x40000;
72/** The request was an instruction read. */
73const uint32_t INST_READ = 0x80000;
74/** This request is for a memory swap. */
75const uint32_t MEM_SWAP = 0x100000;
76const uint32_t MEM_SWAP_COND = 0x200000;
77
78
43#include "sim/host.hh"
44#include "sim/core.hh"
45
46#include <cassert>
47
48class Request;
49
50typedef Request* RequestPtr;

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72const uint32_t NO_ALIGN_FAULT = 0x40000;
73/** The request was an instruction read. */
74const uint32_t INST_READ = 0x80000;
75/** This request is for a memory swap. */
76const uint32_t MEM_SWAP = 0x100000;
77const uint32_t MEM_SWAP_COND = 0x200000;
78
79
79class Request
80class Request : public FastAlloc
80{
81 private:
82 /**
83 * The physical address of the request. Valid only if validPaddr
84 * is set. */
85 Addr paddr;
86
87 /**

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148
149 Request(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc,
150 int _cpuNum, int _threadNum)
151 {
152 setThreadContext(_cpuNum, _threadNum);
153 setVirt(_asid, _vaddr, _size, _flags, _pc);
154 }
155
81{
82 private:
83 /**
84 * The physical address of the request. Valid only if validPaddr
85 * is set. */
86 Addr paddr;
87
88 /**

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149
150 Request(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc,
151 int _cpuNum, int _threadNum)
152 {
153 setThreadContext(_cpuNum, _threadNum);
154 setVirt(_asid, _vaddr, _size, _flags, _pc);
155 }
156
157 ~Request() {} // for FastAlloc
158
156 /**
157 * Set up CPU and thread numbers. */
158 void setThreadContext(int _cpuNum, int _threadNum)
159 {
160 cpuNum = _cpuNum;
161 threadNum = _threadNum;
162 validCpuAndThreadNums = true;
163 }

--- 113 unchanged lines hidden --- 		159 /**
160 * Set up CPU and thread numbers. */
161 void setThreadContext(int _cpuNum, int _threadNum)
162 {
163 cpuNum = _cpuNum;
164 threadNum = _threadNum;
165 validCpuAndThreadNums = true;
166 }

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