request.hh (11305:78c1e4f5dfc5) request.hh (11306:a5340a2a24f9)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158 /** The request should be marked with ACQUIRE. */
159 ACQUIRE = 0x00020000,
160 /** The request should be marked with RELEASE. */
161 RELEASE = 0x00040000,
162
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158 /** The request should be marked with ACQUIRE. */
159 ACQUIRE = 0x00020000,
160 /** The request should be marked with RELEASE. */
161 RELEASE = 0x00040000,
162
163 /** The request is an atomic that returns data. */
164 ATOMIC_RETURN_OP = 0x40000000,
165 /** The request is an atomic that does not return data. */
166 ATOMIC_NO_RETURN_OP = 0x80000000,
167
163 /** The request should be marked with KERNEL.
164 * Used to indicate the synchronization associated with a GPU kernel
165 * launch or completion.
166 */
167 KERNEL = 0x00001000,
168
169 /**
170 * The request should be handled by the generic IPR code (only

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340 ThreadID _threadId;
341
342 /** program counter of initiating access; for tracing/debugging */
343 Addr _pc;
344
345 /** Sequence number of the instruction that creates the request */
346 InstSeqNum _reqInstSeqNum;
347
168 /** The request should be marked with KERNEL.
169 * Used to indicate the synchronization associated with a GPU kernel
170 * launch or completion.
171 */
172 KERNEL = 0x00001000,
173
174 /**
175 * The request should be handled by the generic IPR code (only

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345 ThreadID _threadId;
346
347 /** program counter of initiating access; for tracing/debugging */
348 Addr _pc;
349
350 /** Sequence number of the instruction that creates the request */
351 InstSeqNum _reqInstSeqNum;
352
353 /** A pointer to an atomic operation */
354 AtomicOpFunctor *atomicOpFunctor;
355
348 public:
349
350 /**
351 * Minimal constructor. No fields are initialized. (Note that
352 * _flags and privateFlags are cleared by Flags default
353 * constructor.)
354 */
355 Request()
356 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
357 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
358 _extraData(0), _contextId(0), _threadId(0), _pc(0),
356 public:
357
358 /**
359 * Minimal constructor. No fields are initialized. (Note that
360 * _flags and privateFlags are cleared by Flags default
361 * constructor.)
362 */
363 Request()
364 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
365 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
366 _extraData(0), _contextId(0), _threadId(0), _pc(0),
359 _reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
367 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
368 accessDelta(0), depth(0)
360 {}
361
362 Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
363 InstSeqNum seq_num, ContextID cid, ThreadID tid)
364 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
365 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
366 _extraData(0), _contextId(0), _threadId(0), _pc(0),
369 {}
370
371 Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
372 InstSeqNum seq_num, ContextID cid, ThreadID tid)
373 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
374 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
375 _extraData(0), _contextId(0), _threadId(0), _pc(0),
367 _reqInstSeqNum(seq_num), translateDelta(0), accessDelta(0), depth(0)
376 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
377 accessDelta(0), depth(0)
368 {
369 setPhys(paddr, size, flags, mid, curTick());
370 setThreadContext(cid, tid);
371 privateFlags.set(VALID_INST_SEQ_NUM);
372 }
373
374 /**
375 * Constructor for physical (e.g. device) requests. Initializes
376 * just physical address, size, flags, and timestamp (to curTick()).
377 * These fields are adequate to perform a request.
378 */
379 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
380 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
381 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
382 _extraData(0), _contextId(0), _threadId(0), _pc(0),
378 {
379 setPhys(paddr, size, flags, mid, curTick());
380 setThreadContext(cid, tid);
381 privateFlags.set(VALID_INST_SEQ_NUM);
382 }
383
384 /**
385 * Constructor for physical (e.g. device) requests. Initializes
386 * just physical address, size, flags, and timestamp (to curTick()).
387 * These fields are adequate to perform a request.
388 */
389 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
390 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
391 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
392 _extraData(0), _contextId(0), _threadId(0), _pc(0),
383 _reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
393 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
394 accessDelta(0), depth(0)
384 {
385 setPhys(paddr, size, flags, mid, curTick());
386 }
387
388 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
389 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
390 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
391 _extraData(0), _contextId(0), _threadId(0), _pc(0),
395 {
396 setPhys(paddr, size, flags, mid, curTick());
397 }
398
399 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
400 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
401 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
402 _extraData(0), _contextId(0), _threadId(0), _pc(0),
392 _reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
403 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
404 accessDelta(0), depth(0)
393 {
394 setPhys(paddr, size, flags, mid, time);
395 }
396
397 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
398 Addr pc)
399 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
400 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
405 {
406 setPhys(paddr, size, flags, mid, time);
407 }
408
409 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
410 Addr pc)
411 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
412 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
401 _extraData(0), _contextId(0), _threadId(0), _pc(0),
402 _reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
413 _extraData(0), _contextId(0), _threadId(0), _pc(pc),
414 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
415 accessDelta(0), depth(0)
403 {
404 setPhys(paddr, size, flags, mid, time);
405 privateFlags.set(VALID_PC);
416 {
417 setPhys(paddr, size, flags, mid, time);
418 privateFlags.set(VALID_PC);
406 _pc = pc;
407 }
408
409 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
410 Addr pc, ContextID cid, ThreadID tid)
411 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
412 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
413 _extraData(0), _contextId(0), _threadId(0), _pc(0),
419 }
420
421 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
422 Addr pc, ContextID cid, ThreadID tid)
423 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
424 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
425 _extraData(0), _contextId(0), _threadId(0), _pc(0),
414 _reqInstSeqNum(0), translateDelta(0), accessDelta(0), depth(0)
426 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
427 accessDelta(0), depth(0)
415 {
416 setVirt(asid, vaddr, size, flags, mid, pc);
417 setThreadContext(cid, tid);
418 }
419
428 {
429 setVirt(asid, vaddr, size, flags, mid, pc);
430 setThreadContext(cid, tid);
431 }
432
420 ~Request() {}
433 Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
434 int cid, ThreadID tid, AtomicOpFunctor *atomic_op)
435 : atomicOpFunctor(atomic_op)
436 {
437 setVirt(asid, vaddr, size, flags, mid, pc);
438 setThreadContext(cid, tid);
439 }
421
440
441 ~Request()
442 {
443 if (hasAtomicOpFunctor()) {
444 delete atomicOpFunctor;
445 }
446 }
447
422 /**
423 * Set up CPU and thread numbers.
424 */
425 void
426 setThreadContext(ContextID context_id, ThreadID tid)
427 {
428 _contextId = context_id;
429 _threadId = tid;

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536 /** Accessor for time. */
537 Tick
538 time() const
539 {
540 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
541 return _time;
542 }
543
448 /**
449 * Set up CPU and thread numbers.
450 */
451 void
452 setThreadContext(ContextID context_id, ThreadID tid)
453 {
454 _contextId = context_id;
455 _threadId = tid;

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562 /** Accessor for time. */
563 Tick
564 time() const
565 {
566 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
567 return _time;
568 }
569
570 /**
571 * Accessor for atomic-op functor.
572 */
573 bool
574 hasAtomicOpFunctor()
575 {
576 return atomicOpFunctor != NULL;
577 }
578
579 AtomicOpFunctor *
580 getAtomicOpFunctor()
581 {
582 assert(atomicOpFunctor != NULL);
583 return atomicOpFunctor;
584 }
585
544 /** Accessor for flags. */
545 Flags
546 getFlags()
547 {
548 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
549 return _flags;
550 }
551

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744 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
745 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
746 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
747 bool isSecure() const { return _flags.isSet(SECURE); }
748 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
749 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
750 bool isRelease() const { return _flags.isSet(RELEASE); }
751 bool isKernel() const { return _flags.isSet(KERNEL); }
586 /** Accessor for flags. */
587 Flags
588 getFlags()
589 {
590 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
591 return _flags;
592 }
593

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786 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
787 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
788 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
789 bool isSecure() const { return _flags.isSet(SECURE); }
790 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
791 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
792 bool isRelease() const { return _flags.isSet(RELEASE); }
793 bool isKernel() const { return _flags.isSet(KERNEL); }
794 bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
795 bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
752
796
797 bool
798 isAtomic() const
799 {
800 return _flags.isSet(ATOMIC_RETURN_OP) ||
801 _flags.isSet(ATOMIC_NO_RETURN_OP);
802 }
803
753 /**
754 * Accessor functions for the memory space configuration flags and used by
755 * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
756 * these are for testing only; setting extraFlags should be done via
757 * setMemSpaceConfigFlags().
758 */
759 bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
760

--- 75 unchanged lines hidden --- 		804 /**
805 * Accessor functions for the memory space configuration flags and used by
806 * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
807 * these are for testing only; setting extraFlags should be done via
808 * setMemSpaceConfigFlags().
809 */
810 bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
811

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