1/* 2 * Copyright (c) 2012-2013,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ron Dreslinski 42 * Steve Reinhardt 43 * Ali Saidi 44 */ 45 46/** 47 * @file 48 * Declaration of a request, the overall memory request consisting of 49 the parts of the request that are persistent throughout the transaction. 50 */ 51 52#ifndef __MEM_REQUEST_HH__ 53#define __MEM_REQUEST_HH__ 54 55#include <cassert> 56#include <climits> 57 58#include "base/flags.hh" 59#include "base/logging.hh" 60#include "base/types.hh" 61#include "cpu/inst_seq.hh" 62#include "sim/core.hh" 63 64/** 65 * Special TaskIds that are used for per-context-switch stats dumps 66 * and Cache Occupancy. Having too many tasks seems to be a problem 67 * with vector stats. 1024 seems to be a reasonable number that 68 * doesn't cause a problem with stats and is large enough to realistic 69 * benchmarks (Linux/Android boot, BBench, etc.) 70 */ 71 72namespace ContextSwitchTaskId { 73 enum TaskId { 74 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */ 75 Prefetcher = 1022, /* For cache lines brought in by prefetcher */ 76 DMA = 1023, /* Mostly Table Walker */ 77 Unknown = 1024, 78 NumTaskId 79 }; 80} 81 82class Request; 83 84typedef std::shared_ptr<Request> RequestPtr; 85typedef uint16_t MasterID; 86 87class Request 88{ 89 public: 90 typedef uint64_t FlagsType; 91 typedef uint8_t ArchFlagsType; 92 typedef ::Flags<FlagsType> Flags; 93 94 enum : FlagsType { 95 /** 96 * Architecture specific flags. 97 * 98 * These bits int the flag field are reserved for 99 * architecture-specific code. For example, SPARC uses them to 100 * represent ASIs. 101 */ 102 ARCH_BITS = 0x000000FF, 103 /** The request was an instruction fetch. */ 104 INST_FETCH = 0x00000100, 105 /** The virtual address is also the physical address. */ 106 PHYSICAL = 0x00000200, 107 /** 108 * The request is to an uncacheable address. 109 * 110 * @note Uncacheable accesses may be reordered by CPU models. The 111 * STRICT_ORDER flag should be set if such reordering is 112 * undesirable. 113 */ 114 UNCACHEABLE = 0x00000400, 115 /** 116 * The request is required to be strictly ordered by <i>CPU 117 * models</i> and is non-speculative. 118 * 119 * A strictly ordered request is guaranteed to never be 120 * re-ordered or executed speculatively by a CPU model. The 121 * memory system may still reorder requests in caches unless 122 * the UNCACHEABLE flag is set as well. 123 */ 124 STRICT_ORDER = 0x00000800, 125 /** This request is to a memory mapped register. */ 126 MMAPPED_IPR = 0x00002000, 127 /** This request is made in privileged mode. */ 128 PRIVILEGED = 0x00008000, 129 130 /** 131 * This is a write that is targeted and zeroing an entire 132 * cache block. There is no need for a read/modify/write 133 */ 134 CACHE_BLOCK_ZERO = 0x00010000, 135 136 /** The request should not cause a memory access. */ 137 NO_ACCESS = 0x00080000, 138 /** 139 * This request will lock or unlock the accessed memory. When 140 * used with a load, the access locks the particular chunk of 141 * memory. When used with a store, it unlocks. The rule is 142 * that locked accesses have to be made up of a locked load, 143 * some operation on the data, and then a locked store. 144 */ 145 LOCKED_RMW = 0x00100000, 146 /** The request is a Load locked/store conditional. */ 147 LLSC = 0x00200000, 148 /** This request is for a memory swap. */ 149 MEM_SWAP = 0x00400000, 150 MEM_SWAP_COND = 0x00800000, 151 152 /** The request is a prefetch. */ 153 PREFETCH = 0x01000000, 154 /** The request should be prefetched into the exclusive state. */ 155 PF_EXCLUSIVE = 0x02000000, 156 /** The request should be marked as LRU. */ 157 EVICT_NEXT = 0x04000000, 158 /** The request should be marked with ACQUIRE. */ 159 ACQUIRE = 0x00020000, 160 /** The request should be marked with RELEASE. */ 161 RELEASE = 0x00040000, 162 163 /** The request is an atomic that returns data. */ 164 ATOMIC_RETURN_OP = 0x40000000, 165 /** The request is an atomic that does not return data. */ 166 ATOMIC_NO_RETURN_OP = 0x80000000, 167 168 /** The request should be marked with KERNEL. 169 * Used to indicate the synchronization associated with a GPU kernel 170 * launch or completion. 171 */ 172 KERNEL = 0x00001000, 173 174 /** 175 * The request should be handled by the generic IPR code (only 176 * valid together with MMAPPED_IPR) 177 */ 178 GENERIC_IPR = 0x08000000, 179 180 /** The request targets the secure memory space. */ 181 SECURE = 0x10000000, 182 /** The request is a page table walk */ 183 PT_WALK = 0x20000000, 184 185 /** The request invalidates a memory location */ 186 INVALIDATE = 0x0000000100000000, 187 /** The request cleans a memory location */ 188 CLEAN = 0x0000000200000000, 189 190 /** The request targets the point of unification */ 191 DST_POU = 0x0000001000000000, 192 193 /** The request targets the point of coherence */ 194 DST_POC = 0x0000002000000000, 195 196 /** Bits to define the destination of a request */ 197 DST_BITS = 0x0000003000000000, 198 199 /** 200 * These flags are *not* cleared when a Request object is 201 * reused (assigned a new address). 202 */ 203 STICKY_FLAGS = INST_FETCH 204 }; 205 static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO | 206 CLEAN | INVALIDATE; 207 208 /** Master Ids that are statically allocated 209 * @{*/ 210 enum : MasterID { 211 /** This master id is used for writeback requests by the caches */ 212 wbMasterId = 0, 213 /** 214 * This master id is used for functional requests that 215 * don't come from a particular device 216 */ 217 funcMasterId = 1, 218 /** This master id is used for message signaled interrupts */ 219 intMasterId = 2, 220 /** 221 * Invalid master id for assertion checking only. It is 222 * invalid behavior to ever send this id as part of a request. 223 */ 224 invldMasterId = std::numeric_limits<MasterID>::max() 225 }; 226 /** @} */ 227 228 typedef uint32_t MemSpaceConfigFlagsType; 229 typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags; 230 231 enum : MemSpaceConfigFlagsType { 232 /** Has a synchronization scope been set? */ 233 SCOPE_VALID = 0x00000001, 234 /** Access has Wavefront scope visibility */ 235 WAVEFRONT_SCOPE = 0x00000002, 236 /** Access has Workgroup scope visibility */ 237 WORKGROUP_SCOPE = 0x00000004, 238 /** Access has Device (e.g., GPU) scope visibility */ 239 DEVICE_SCOPE = 0x00000008, 240 /** Access has System (e.g., CPU + GPU) scope visibility */ 241 SYSTEM_SCOPE = 0x00000010, 242 243 /** Global Segment */ 244 GLOBAL_SEGMENT = 0x00000020, 245 /** Group Segment */ 246 GROUP_SEGMENT = 0x00000040, 247 /** Private Segment */ 248 PRIVATE_SEGMENT = 0x00000080, 249 /** Kergarg Segment */ 250 KERNARG_SEGMENT = 0x00000100, 251 /** Readonly Segment */ 252 READONLY_SEGMENT = 0x00000200, 253 /** Spill Segment */ 254 SPILL_SEGMENT = 0x00000400, 255 /** Arg Segment */ 256 ARG_SEGMENT = 0x00000800, 257 }; 258 259 private: 260 typedef uint8_t PrivateFlagsType; 261 typedef ::Flags<PrivateFlagsType> PrivateFlags; 262 263 enum : PrivateFlagsType { 264 /** Whether or not the size is valid. */ 265 VALID_SIZE = 0x00000001, 266 /** Whether or not paddr is valid (has been written yet). */ 267 VALID_PADDR = 0x00000002, 268 /** Whether or not the vaddr & asid are valid. */ 269 VALID_VADDR = 0x00000004, 270 /** Whether or not the instruction sequence number is valid. */ 271 VALID_INST_SEQ_NUM = 0x00000008, 272 /** Whether or not the pc is valid. */ 273 VALID_PC = 0x00000010, 274 /** Whether or not the context ID is valid. */ 275 VALID_CONTEXT_ID = 0x00000020, 276 /** Whether or not the sc result is valid. */ 277 VALID_EXTRA_DATA = 0x00000080, 278 /** 279 * These flags are *not* cleared when a Request object is reused 280 * (assigned a new address). 281 */ 282 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID 283 }; 284 285 private: 286 287 /** 288 * Set up a physical (e.g. device) request in a previously 289 * allocated Request object. 290 */ 291 void 292 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 293 { 294 _paddr = paddr; 295 _size = size; 296 _time = time; 297 _masterId = mid; 298 _flags.clear(~STICKY_FLAGS); 299 _flags.set(flags); 300 privateFlags.clear(~STICKY_PRIVATE_FLAGS); 301 privateFlags.set(VALID_PADDR|VALID_SIZE); 302 depth = 0; 303 accessDelta = 0; 304 //translateDelta = 0; 305 } 306 307 /** 308 * The physical address of the request. Valid only if validPaddr 309 * is set. 310 */ 311 Addr _paddr; 312 313 /** 314 * The size of the request. This field must be set when vaddr or 315 * paddr is written via setVirt() or setPhys(), so it is always 316 * valid as long as one of the address fields is valid. 317 */ 318 unsigned _size; 319 320 /** The requestor ID which is unique in the system for all ports 321 * that are capable of issuing a transaction 322 */ 323 MasterID _masterId; 324 325 /** Flag structure for the request. */ 326 Flags _flags; 327 328 /** Memory space configuraiton flag structure for the request. */ 329 MemSpaceConfigFlags _memSpaceConfigFlags; 330 331 /** Private flags for field validity checking. */ 332 PrivateFlags privateFlags; 333 334 /** 335 * The time this request was started. Used to calculate 336 * latencies. This field is set to curTick() any time paddr or vaddr 337 * is written. 338 */ 339 Tick _time; 340 341 /** 342 * The task id associated with this request 343 */ 344 uint32_t _taskId; 345 346 /** The address space ID. */ 347 int _asid; 348 349 /** The virtual address of the request. */ 350 Addr _vaddr; 351 352 /** 353 * Extra data for the request, such as the return value of 354 * store conditional or the compare value for a CAS. */ 355 uint64_t _extraData; 356 357 /** The context ID (for statistics, locks, and wakeups). */ 358 ContextID _contextId; 359 360 /** program counter of initiating access; for tracing/debugging */ 361 Addr _pc; 362 363 /** Sequence number of the instruction that creates the request */ 364 InstSeqNum _reqInstSeqNum; 365 366 /** A pointer to an atomic operation */ 367 AtomicOpFunctor *atomicOpFunctor; 368 369 public: 370 371 /** 372 * Minimal constructor. No fields are initialized. (Note that 373 * _flags and privateFlags are cleared by Flags default 374 * constructor.) 375 */ 376 Request() 377 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 378 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 379 _extraData(0), _contextId(0), _pc(0), 380 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 381 accessDelta(0), depth(0) 382 {} 383 384 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, 385 InstSeqNum seq_num, ContextID cid) 386 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 387 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 388 _extraData(0), _contextId(0), _pc(0), 389 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0), 390 accessDelta(0), depth(0) 391 { 392 setPhys(paddr, size, flags, mid, curTick()); 393 setContext(cid); 394 privateFlags.set(VALID_INST_SEQ_NUM); 395 } 396 397 /** 398 * Constructor for physical (e.g. device) requests. Initializes 399 * just physical address, size, flags, and timestamp (to curTick()). 400 * These fields are adequate to perform a request. 401 */ 402 Request(Addr paddr, unsigned size, Flags flags, MasterID mid) 403 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 404 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 405 _extraData(0), _contextId(0), _pc(0), 406 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 407 accessDelta(0), depth(0) 408 { 409 setPhys(paddr, size, flags, mid, curTick()); 410 } 411 412 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 413 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 414 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 415 _extraData(0), _contextId(0), _pc(0), 416 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 417 accessDelta(0), depth(0) 418 { 419 setPhys(paddr, size, flags, mid, time); 420 } 421 422 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time, 423 Addr pc) 424 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 425 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 426 _extraData(0), _contextId(0), _pc(pc), 427 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 428 accessDelta(0), depth(0) 429 { 430 setPhys(paddr, size, flags, mid, time); 431 privateFlags.set(VALID_PC); 432 } 433 434 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 435 Addr pc, ContextID cid) 436 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), 437 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), 438 _extraData(0), _contextId(0), _pc(0), 439 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0), 440 accessDelta(0), depth(0) 441 { 442 setVirt(asid, vaddr, size, flags, mid, pc); 443 setContext(cid); 444 } 445 446 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, 447 Addr pc, ContextID cid, AtomicOpFunctor *atomic_op)
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