1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37 */ 38 39#ifndef __MEM_REQUEST_HH__ 40#define __MEM_REQUEST_HH__ 41 42#include <cassert> 43#include <climits> 44 |
45#include "base/flags.hh" 46#include "base/misc.hh" 47#include "base/types.hh" 48#include "sim/core.hh" 49 50class Request; 51 52typedef Request* RequestPtr; 53typedef uint16_t MasterID; 54 |
55class Request |
56{ 57 public: 58 typedef uint32_t FlagsType; 59 typedef ::Flags<FlagsType> Flags; 60 61 /** ASI information for this request if it exists. */ 62 static const FlagsType ASI_BITS = 0x000000FF; 63 /** The request was an instruction fetch. */ --- 159 unchanged lines hidden (view full) --- 223 224 Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc, 225 int cid, ThreadID tid) 226 { 227 setVirt(asid, vaddr, size, flags, mid, pc); 228 setThreadContext(cid, tid); 229 } 230 |
231 ~Request() {} |
232 233 /** 234 * Set up CPU and thread numbers. 235 */ 236 void 237 setThreadContext(int context_id, ThreadID tid) 238 { 239 _contextId = context_id; --- 258 unchanged lines hidden --- |