2c2
< * Copyright (c) 2012 ARM Limited
---
> * Copyright (c) 2012-2013 ARM Limited
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> : translateDelta(0), accessDelta(0), depth(0)
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> depth = 0;
> accessDelta = 0;
> //translateDelta = 0;
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> depth = 0;
> accessDelta = 0;
> translateDelta = 0;
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> * Time for the TLB/table walker to successfully translate this request.
> */
> Tick translateDelta;
>
> /**
> * Access latency to complete this memory transaction not including
> * translation time.
> */
> Tick accessDelta;
>
> /**
> * Level of the cache hierachy where this request was responded to
> * (e.g. 0 = L1; 1 = L2).
> */
> int depth;
>
> /**
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> /**
> * Increment/Get the depth at which this request is responded to.
> * This currently happens when the request misses in any cache level.
> */
> void incAccessDepth() { depth++; }
> int getAccessDepth() const { return depth; }
>
> /**
> * Set/Get the time taken for this request to be successfully translated.
> */
> void setTranslateLatency() { translateDelta = curTick() - _time; }
> Tick getTranslateLatency() const { return translateDelta; }
>
> /**
> * Set/Get the time taken to complete this request's access, not including
> * the time to successfully translate the request.
> */
> void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
> Tick getAccessLatency() const { return accessDelta; }
>