1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
|
| 15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
|
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 * Ali Saidi
43 */
44
45/**
46 * @file
47 * Declaration of a request, the overall memory request consisting of
48 the parts of the request that are persistent throughout the transaction.
49 */
50
51#ifndef __MEM_REQUEST_HH__
52#define __MEM_REQUEST_HH__
53
54#include <cassert>
55#include <climits>
56
57#include "base/flags.hh"
58#include "base/misc.hh"
59#include "base/types.hh"
60#include "sim/core.hh"
61
62/**
63 * Special TaskIds that are used for per-context-switch stats dumps
64 * and Cache Occupancy. Having too many tasks seems to be a problem
65 * with vector stats. 1024 seems to be a reasonable number that
66 * doesn't cause a problem with stats and is large enough to realistic
67 * benchmarks (Linux/Android boot, BBench, etc.)
68 */
69
70namespace ContextSwitchTaskId {
71 enum TaskId {
72 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
73 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
74 DMA = 1023, /* Mostly Table Walker */
75 Unknown = 1024,
76 NumTaskId
77 };
78}
79
80class Request;
81
82typedef Request* RequestPtr;
83typedef uint16_t MasterID;
84
85class Request
86{
87 public:
| 16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ron Dreslinski
42 * Steve Reinhardt
43 * Ali Saidi
44 */
45
46/**
47 * @file
48 * Declaration of a request, the overall memory request consisting of
49 the parts of the request that are persistent throughout the transaction.
50 */
51
52#ifndef __MEM_REQUEST_HH__
53#define __MEM_REQUEST_HH__
54
55#include <cassert>
56#include <climits>
57
58#include "base/flags.hh"
59#include "base/misc.hh"
60#include "base/types.hh"
61#include "sim/core.hh"
62
63/**
64 * Special TaskIds that are used for per-context-switch stats dumps
65 * and Cache Occupancy. Having too many tasks seems to be a problem
66 * with vector stats. 1024 seems to be a reasonable number that
67 * doesn't cause a problem with stats and is large enough to realistic
68 * benchmarks (Linux/Android boot, BBench, etc.)
69 */
70
71namespace ContextSwitchTaskId {
72 enum TaskId {
73 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
74 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
75 DMA = 1023, /* Mostly Table Walker */
76 Unknown = 1024,
77 NumTaskId
78 };
79}
80
81class Request;
82
83typedef Request* RequestPtr;
84typedef uint16_t MasterID;
85
86class Request
87{
88 public:
|
88 typedef uint32_t FlagsType;
| 89 typedef uint64_t FlagsType;
|
89 typedef uint8_t ArchFlagsType;
90 typedef ::Flags<FlagsType> Flags;
91
92 enum : FlagsType {
93 /**
94 * Architecture specific flags.
95 *
96 * These bits int the flag field are reserved for
97 * architecture-specific code. For example, SPARC uses them to
98 * represent ASIs.
99 */
| 90 typedef uint8_t ArchFlagsType;
91 typedef ::Flags<FlagsType> Flags;
92
93 enum : FlagsType {
94 /**
95 * Architecture specific flags.
96 *
97 * These bits int the flag field are reserved for
98 * architecture-specific code. For example, SPARC uses them to
99 * represent ASIs.
100 */
|
100 ARCH_BITS = 0x000000FF,
| 101 ARCH_BITS = 0x00000000000000FF,
|
101 /** The request was an instruction fetch. */
| 102 /** The request was an instruction fetch. */
|
102 INST_FETCH = 0x00000100,
| 103 INST_FETCH = 0x0000000000000100,
|
103 /** The virtual address is also the physical address. */
| 104 /** The virtual address is also the physical address. */
|
104 PHYSICAL = 0x00000200,
| 105 PHYSICAL = 0x0000000000000200,
|
105 /**
106 * The request is to an uncacheable address.
107 *
108 * @note Uncacheable accesses may be reordered by CPU models. The
109 * STRICT_ORDER flag should be set if such reordering is
110 * undesirable.
111 */
| 106 /**
107 * The request is to an uncacheable address.
108 *
109 * @note Uncacheable accesses may be reordered by CPU models. The
110 * STRICT_ORDER flag should be set if such reordering is
111 * undesirable.
112 */
|
112 UNCACHEABLE = 0x00000400,
| 113 UNCACHEABLE = 0x0000000000000400,
|
113 /**
114 * The request is required to be strictly ordered by <i>CPU
115 * models</i> and is non-speculative.
116 *
117 * A strictly ordered request is guaranteed to never be
118 * re-ordered or executed speculatively by a CPU model. The
119 * memory system may still reorder requests in caches unless
120 * the UNCACHEABLE flag is set as well.
121 */
| 114 /**
115 * The request is required to be strictly ordered by <i>CPU
116 * models</i> and is non-speculative.
117 *
118 * A strictly ordered request is guaranteed to never be
119 * re-ordered or executed speculatively by a CPU model. The
120 * memory system may still reorder requests in caches unless
121 * the UNCACHEABLE flag is set as well.
122 */
|
122 STRICT_ORDER = 0x00000800,
| 123 STRICT_ORDER = 0x0000000000000800,
|
123 /** This request is to a memory mapped register. */
| 124 /** This request is to a memory mapped register. */
|
124 MMAPPED_IPR = 0x00002000,
| 125 MMAPPED_IPR = 0x0000000000001000,
|
125 /** This request is a clear exclusive. */
| 126 /** This request is a clear exclusive. */
|
126 CLEAR_LL = 0x00004000,
| 127 CLEAR_LL = 0x0000000000002000,
|
127 /** This request is made in privileged mode. */
| 128 /** This request is made in privileged mode. */
|
128 PRIVILEGED = 0x00008000,
| 129 PRIVILEGED = 0x0000000000004000,
|
129
130 /**
131 * This is a write that is targeted and zeroing an entire
132 * cache block. There is no need for a read/modify/write
133 */
| 130
131 /**
132 * This is a write that is targeted and zeroing an entire
133 * cache block. There is no need for a read/modify/write
134 */
|
134 CACHE_BLOCK_ZERO = 0x00010000,
| 135 CACHE_BLOCK_ZERO = 0x0000000000008000,
|
135
136 /** The request should not cause a memory access. */
| 136
137 /** The request should not cause a memory access. */
|
137 NO_ACCESS = 0x00080000,
| 138 NO_ACCESS = 0x0000000000100000,
|
138 /**
139 * This request will lock or unlock the accessed memory. When
140 * used with a load, the access locks the particular chunk of
141 * memory. When used with a store, it unlocks. The rule is
142 * that locked accesses have to be made up of a locked load,
143 * some operation on the data, and then a locked store.
144 */
| 139 /**
140 * This request will lock or unlock the accessed memory. When
141 * used with a load, the access locks the particular chunk of
142 * memory. When used with a store, it unlocks. The rule is
143 * that locked accesses have to be made up of a locked load,
144 * some operation on the data, and then a locked store.
145 */
|
145 LOCKED_RMW = 0x00100000,
| 146 LOCKED_RMW = 0x0000000000200000,
|
146 /** The request is a Load locked/store conditional. */
| 147 /** The request is a Load locked/store conditional. */
|
147 LLSC = 0x00200000,
| 148 LLSC = 0x0000000000400000,
|
148 /** This request is for a memory swap. */
| 149 /** This request is for a memory swap. */
|
149 MEM_SWAP = 0x00400000,
150 MEM_SWAP_COND = 0x00800000,
| 150 MEM_SWAP = 0x0000000000800000,
151 MEM_SWAP_COND = 0x0000000001000000,
|
151
152 /** The request is a prefetch. */
| 152
153 /** The request is a prefetch. */
|
153 PREFETCH = 0x01000000,
| 154 PREFETCH = 0x0000000002000000,
|
154 /** The request should be prefetched into the exclusive state. */
| 155 /** The request should be prefetched into the exclusive state. */
|
155 PF_EXCLUSIVE = 0x02000000,
| 156 PF_EXCLUSIVE = 0x0000000004000000,
|
156 /** The request should be marked as LRU. */
| 157 /** The request should be marked as LRU. */
|
157 EVICT_NEXT = 0x04000000,
| 158 EVICT_NEXT = 0x0000000008000000,
159 /** The request should be marked with ACQUIRE. */
160 ACQUIRE = 0x0000000001000000,
161 /** The request should be marked with RELEASE. */
162 RELEASE = 0x0000000002000000,
|
158
159 /**
160 * The request should be handled by the generic IPR code (only
161 * valid together with MMAPPED_IPR)
162 */
| 163
164 /**
165 * The request should be handled by the generic IPR code (only
166 * valid together with MMAPPED_IPR)
167 */
|
163 GENERIC_IPR = 0x08000000,
| 168 GENERIC_IPR = 0x0000000004000000,
|
164
165 /** The request targets the secure memory space. */
| 169
170 /** The request targets the secure memory space. */
|
166 SECURE = 0x10000000,
| 171 SECURE = 0x0000000008000000,
|
167 /** The request is a page table walk */
| 172 /** The request is a page table walk */
|
168 PT_WALK = 0x20000000,
| 173 PT_WALK = 0x0000000010000000,
|
169
170 /**
171 * These flags are *not* cleared when a Request object is
172 * reused (assigned a new address).
173 */
174 STICKY_FLAGS = INST_FETCH
175 };
176
177 /** Master Ids that are statically allocated
178 * @{*/
179 enum : MasterID {
180 /** This master id is used for writeback requests by the caches */
181 wbMasterId = 0,
182 /**
183 * This master id is used for functional requests that
184 * don't come from a particular device
185 */
186 funcMasterId = 1,
187 /** This master id is used for message signaled interrupts */
188 intMasterId = 2,
189 /**
190 * Invalid master id for assertion checking only. It is
191 * invalid behavior to ever send this id as part of a request.
192 */
193 invldMasterId = std::numeric_limits<MasterID>::max()
194 };
195 /** @} */
196
197 /** Invalid or unknown Pid. Possible when operating system is not present
198 * or has not assigned a pid yet */
199 static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
200
201 private:
202 typedef uint8_t PrivateFlagsType;
203 typedef ::Flags<PrivateFlagsType> PrivateFlags;
204
205 enum : PrivateFlagsType {
206 /** Whether or not the size is valid. */
207 VALID_SIZE = 0x00000001,
208 /** Whether or not paddr is valid (has been written yet). */
209 VALID_PADDR = 0x00000002,
210 /** Whether or not the vaddr & asid are valid. */
211 VALID_VADDR = 0x00000004,
212 /** Whether or not the pc is valid. */
213 VALID_PC = 0x00000010,
214 /** Whether or not the context ID is valid. */
215 VALID_CONTEXT_ID = 0x00000020,
216 VALID_THREAD_ID = 0x00000040,
217 /** Whether or not the sc result is valid. */
218 VALID_EXTRA_DATA = 0x00000080,
219
220 /**
221 * These flags are *not* cleared when a Request object is reused
222 * (assigned a new address).
223 */
224 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
225 };
226
227 private:
228
229 /**
230 * Set up a physical (e.g. device) request in a previously
231 * allocated Request object.
232 */
233 void
234 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
235 {
236 assert(size >= 0);
237 _paddr = paddr;
238 _size = size;
239 _time = time;
240 _masterId = mid;
241 _flags.clear(~STICKY_FLAGS);
242 _flags.set(flags);
243 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
244 privateFlags.set(VALID_PADDR|VALID_SIZE);
245 depth = 0;
246 accessDelta = 0;
247 //translateDelta = 0;
248 }
249
250 /**
251 * The physical address of the request. Valid only if validPaddr
252 * is set.
253 */
254 Addr _paddr;
255
256 /**
257 * The size of the request. This field must be set when vaddr or
258 * paddr is written via setVirt() or setPhys(), so it is always
259 * valid as long as one of the address fields is valid.
260 */
261 unsigned _size;
262
263 /** The requestor ID which is unique in the system for all ports
264 * that are capable of issuing a transaction
265 */
266 MasterID _masterId;
267
268 /** Flag structure for the request. */
269 Flags _flags;
270
271 /** Private flags for field validity checking. */
272 PrivateFlags privateFlags;
273
274 /**
275 * The time this request was started. Used to calculate
276 * latencies. This field is set to curTick() any time paddr or vaddr
277 * is written.
278 */
279 Tick _time;
280
281 /**
282 * The task id associated with this request
283 */
284 uint32_t _taskId;
285
286 /** The address space ID. */
287 int _asid;
288
289 /** The virtual address of the request. */
290 Addr _vaddr;
291
292 /**
293 * Extra data for the request, such as the return value of
294 * store conditional or the compare value for a CAS. */
295 uint64_t _extraData;
296
297 /** The context ID (for statistics, typically). */
298 int _contextId;
299 /** The thread ID (id within this CPU) */
300 ThreadID _threadId;
301
302 /** program counter of initiating access; for tracing/debugging */
303 Addr _pc;
304
305 public:
306
307 /**
308 * Minimal constructor. No fields are initialized. (Note that
309 * _flags and privateFlags are cleared by Flags default
310 * constructor.)
311 */
312 Request()
313 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
314 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
315 _extraData(0), _contextId(0), _threadId(0), _pc(0),
316 translateDelta(0), accessDelta(0), depth(0)
317 {}
318
319 /**
320 * Constructor for physical (e.g. device) requests. Initializes
321 * just physical address, size, flags, and timestamp (to curTick()).
322 * These fields are adequate to perform a request.
323 */
324 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
325 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
326 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
327 _extraData(0), _contextId(0), _threadId(0), _pc(0),
328 translateDelta(0), accessDelta(0), depth(0)
329 {
330 setPhys(paddr, size, flags, mid, curTick());
331 }
332
333 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
334 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
335 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
336 _extraData(0), _contextId(0), _threadId(0), _pc(0),
337 translateDelta(0), accessDelta(0), depth(0)
338 {
339 setPhys(paddr, size, flags, mid, time);
340 }
341
342 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
343 Addr pc)
344 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
345 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
346 _extraData(0), _contextId(0), _threadId(0), _pc(0),
347 translateDelta(0), accessDelta(0), depth(0)
348 {
349 setPhys(paddr, size, flags, mid, time);
350 privateFlags.set(VALID_PC);
351 _pc = pc;
352 }
353
354 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
355 Addr pc, int cid, ThreadID tid)
356 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
357 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
358 _extraData(0), _contextId(0), _threadId(0), _pc(0),
359 translateDelta(0), accessDelta(0), depth(0)
360 {
361 setVirt(asid, vaddr, size, flags, mid, pc);
362 setThreadContext(cid, tid);
363 }
364
365 ~Request() {}
366
367 /**
368 * Set up CPU and thread numbers.
369 */
370 void
371 setThreadContext(int context_id, ThreadID tid)
372 {
373 _contextId = context_id;
374 _threadId = tid;
375 privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
376 }
377
378 /**
379 * Set up a virtual (e.g., CPU) request in a previously
380 * allocated Request object.
381 */
382 void
383 setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
384 Addr pc)
385 {
386 _asid = asid;
387 _vaddr = vaddr;
388 _size = size;
389 _masterId = mid;
390 _pc = pc;
391 _time = curTick();
392
393 _flags.clear(~STICKY_FLAGS);
394 _flags.set(flags);
395 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
396 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
397 depth = 0;
398 accessDelta = 0;
399 translateDelta = 0;
400 }
401
402 /**
403 * Set just the physical address. This usually used to record the
404 * result of a translation. However, when using virtualized CPUs
405 * setPhys() is sometimes called to finalize a physical address
406 * without a virtual address, so we can't check if the virtual
407 * address is valid.
408 */
409 void
410 setPaddr(Addr paddr)
411 {
412 _paddr = paddr;
413 privateFlags.set(VALID_PADDR);
414 }
415
416 /**
417 * Generate two requests as if this request had been split into two
418 * pieces. The original request can't have been translated already.
419 */
420 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
421 {
422 assert(privateFlags.isSet(VALID_VADDR));
423 assert(privateFlags.noneSet(VALID_PADDR));
424 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
425 req1 = new Request(*this);
426 req2 = new Request(*this);
427 req1->_size = split_addr - _vaddr;
428 req2->_vaddr = split_addr;
429 req2->_size = _size - req1->_size;
430 }
431
432 /**
433 * Accessor for paddr.
434 */
435 bool
436 hasPaddr() const
437 {
438 return privateFlags.isSet(VALID_PADDR);
439 }
440
441 Addr
442 getPaddr() const
443 {
444 assert(privateFlags.isSet(VALID_PADDR));
445 return _paddr;
446 }
447
448 /**
449 * Time for the TLB/table walker to successfully translate this request.
450 */
451 Tick translateDelta;
452
453 /**
454 * Access latency to complete this memory transaction not including
455 * translation time.
456 */
457 Tick accessDelta;
458
459 /**
460 * Level of the cache hierachy where this request was responded to
461 * (e.g. 0 = L1; 1 = L2).
462 */
463 mutable int depth;
464
465 /**
466 * Accessor for size.
467 */
468 bool
469 hasSize() const
470 {
471 return privateFlags.isSet(VALID_SIZE);
472 }
473
474 unsigned
475 getSize() const
476 {
477 assert(privateFlags.isSet(VALID_SIZE));
478 return _size;
479 }
480
481 /** Accessor for time. */
482 Tick
483 time() const
484 {
485 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
486 return _time;
487 }
488
489 /** Accessor for flags. */
490 Flags
491 getFlags()
492 {
493 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
494 return _flags;
495 }
496
497 /** Note that unlike other accessors, this function sets *specific
498 flags* (ORs them in); it does not assign its argument to the
499 _flags field. Thus this method should rightly be called
500 setFlags() and not just flags(). */
501 void
502 setFlags(Flags flags)
503 {
504 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
505 _flags.set(flags);
506 }
507
508 /** Accessor function for vaddr.*/
509 bool
510 hasVaddr() const
511 {
512 return privateFlags.isSet(VALID_VADDR);
513 }
514
515 Addr
516 getVaddr() const
517 {
518 assert(privateFlags.isSet(VALID_VADDR));
519 return _vaddr;
520 }
521
522 /** Accesssor for the requestor id. */
523 MasterID
524 masterId() const
525 {
526 return _masterId;
527 }
528
529 uint32_t
530 taskId() const
531 {
532 return _taskId;
533 }
534
535 void
536 taskId(uint32_t id) {
537 _taskId = id;
538 }
539
540 /** Accessor function for asid.*/
541 int
542 getAsid() const
543 {
544 assert(privateFlags.isSet(VALID_VADDR));
545 return _asid;
546 }
547
548 /** Accessor function for asid.*/
549 void
550 setAsid(int asid)
551 {
552 _asid = asid;
553 }
554
555 /** Accessor function for architecture-specific flags.*/
556 ArchFlagsType
557 getArchFlags() const
558 {
559 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
560 return _flags & ARCH_BITS;
561 }
562
563 /** Accessor function to check if sc result is valid. */
564 bool
565 extraDataValid() const
566 {
567 return privateFlags.isSet(VALID_EXTRA_DATA);
568 }
569
570 /** Accessor function for store conditional return value.*/
571 uint64_t
572 getExtraData() const
573 {
574 assert(privateFlags.isSet(VALID_EXTRA_DATA));
575 return _extraData;
576 }
577
578 /** Accessor function for store conditional return value.*/
579 void
580 setExtraData(uint64_t extraData)
581 {
582 _extraData = extraData;
583 privateFlags.set(VALID_EXTRA_DATA);
584 }
585
586 bool
587 hasContextId() const
588 {
589 return privateFlags.isSet(VALID_CONTEXT_ID);
590 }
591
592 /** Accessor function for context ID.*/
593 int
594 contextId() const
595 {
596 assert(privateFlags.isSet(VALID_CONTEXT_ID));
597 return _contextId;
598 }
599
600 /** Accessor function for thread ID. */
601 ThreadID
602 threadId() const
603 {
604 assert(privateFlags.isSet(VALID_THREAD_ID));
605 return _threadId;
606 }
607
608 void
609 setPC(Addr pc)
610 {
611 privateFlags.set(VALID_PC);
612 _pc = pc;
613 }
614
615 bool
616 hasPC() const
617 {
618 return privateFlags.isSet(VALID_PC);
619 }
620
621 /** Accessor function for pc.*/
622 Addr
623 getPC() const
624 {
625 assert(privateFlags.isSet(VALID_PC));
626 return _pc;
627 }
628
629 /**
630 * Increment/Get the depth at which this request is responded to.
631 * This currently happens when the request misses in any cache level.
632 */
633 void incAccessDepth() const { depth++; }
634 int getAccessDepth() const { return depth; }
635
636 /**
637 * Set/Get the time taken for this request to be successfully translated.
638 */
639 void setTranslateLatency() { translateDelta = curTick() - _time; }
640 Tick getTranslateLatency() const { return translateDelta; }
641
642 /**
643 * Set/Get the time taken to complete this request's access, not including
644 * the time to successfully translate the request.
645 */
646 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
647 Tick getAccessLatency() const { return accessDelta; }
648
649 /** Accessor functions for flags. Note that these are for testing
650 only; setting flags should be done via setFlags(). */
651 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
652 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
653 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
654 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
655 bool isLLSC() const { return _flags.isSet(LLSC); }
656 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
657 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
| 174
175 /**
176 * These flags are *not* cleared when a Request object is
177 * reused (assigned a new address).
178 */
179 STICKY_FLAGS = INST_FETCH
180 };
181
182 /** Master Ids that are statically allocated
183 * @{*/
184 enum : MasterID {
185 /** This master id is used for writeback requests by the caches */
186 wbMasterId = 0,
187 /**
188 * This master id is used for functional requests that
189 * don't come from a particular device
190 */
191 funcMasterId = 1,
192 /** This master id is used for message signaled interrupts */
193 intMasterId = 2,
194 /**
195 * Invalid master id for assertion checking only. It is
196 * invalid behavior to ever send this id as part of a request.
197 */
198 invldMasterId = std::numeric_limits<MasterID>::max()
199 };
200 /** @} */
201
202 /** Invalid or unknown Pid. Possible when operating system is not present
203 * or has not assigned a pid yet */
204 static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
205
206 private:
207 typedef uint8_t PrivateFlagsType;
208 typedef ::Flags<PrivateFlagsType> PrivateFlags;
209
210 enum : PrivateFlagsType {
211 /** Whether or not the size is valid. */
212 VALID_SIZE = 0x00000001,
213 /** Whether or not paddr is valid (has been written yet). */
214 VALID_PADDR = 0x00000002,
215 /** Whether or not the vaddr & asid are valid. */
216 VALID_VADDR = 0x00000004,
217 /** Whether or not the pc is valid. */
218 VALID_PC = 0x00000010,
219 /** Whether or not the context ID is valid. */
220 VALID_CONTEXT_ID = 0x00000020,
221 VALID_THREAD_ID = 0x00000040,
222 /** Whether or not the sc result is valid. */
223 VALID_EXTRA_DATA = 0x00000080,
224
225 /**
226 * These flags are *not* cleared when a Request object is reused
227 * (assigned a new address).
228 */
229 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
230 };
231
232 private:
233
234 /**
235 * Set up a physical (e.g. device) request in a previously
236 * allocated Request object.
237 */
238 void
239 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
240 {
241 assert(size >= 0);
242 _paddr = paddr;
243 _size = size;
244 _time = time;
245 _masterId = mid;
246 _flags.clear(~STICKY_FLAGS);
247 _flags.set(flags);
248 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
249 privateFlags.set(VALID_PADDR|VALID_SIZE);
250 depth = 0;
251 accessDelta = 0;
252 //translateDelta = 0;
253 }
254
255 /**
256 * The physical address of the request. Valid only if validPaddr
257 * is set.
258 */
259 Addr _paddr;
260
261 /**
262 * The size of the request. This field must be set when vaddr or
263 * paddr is written via setVirt() or setPhys(), so it is always
264 * valid as long as one of the address fields is valid.
265 */
266 unsigned _size;
267
268 /** The requestor ID which is unique in the system for all ports
269 * that are capable of issuing a transaction
270 */
271 MasterID _masterId;
272
273 /** Flag structure for the request. */
274 Flags _flags;
275
276 /** Private flags for field validity checking. */
277 PrivateFlags privateFlags;
278
279 /**
280 * The time this request was started. Used to calculate
281 * latencies. This field is set to curTick() any time paddr or vaddr
282 * is written.
283 */
284 Tick _time;
285
286 /**
287 * The task id associated with this request
288 */
289 uint32_t _taskId;
290
291 /** The address space ID. */
292 int _asid;
293
294 /** The virtual address of the request. */
295 Addr _vaddr;
296
297 /**
298 * Extra data for the request, such as the return value of
299 * store conditional or the compare value for a CAS. */
300 uint64_t _extraData;
301
302 /** The context ID (for statistics, typically). */
303 int _contextId;
304 /** The thread ID (id within this CPU) */
305 ThreadID _threadId;
306
307 /** program counter of initiating access; for tracing/debugging */
308 Addr _pc;
309
310 public:
311
312 /**
313 * Minimal constructor. No fields are initialized. (Note that
314 * _flags and privateFlags are cleared by Flags default
315 * constructor.)
316 */
317 Request()
318 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
319 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
320 _extraData(0), _contextId(0), _threadId(0), _pc(0),
321 translateDelta(0), accessDelta(0), depth(0)
322 {}
323
324 /**
325 * Constructor for physical (e.g. device) requests. Initializes
326 * just physical address, size, flags, and timestamp (to curTick()).
327 * These fields are adequate to perform a request.
328 */
329 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
330 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
331 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
332 _extraData(0), _contextId(0), _threadId(0), _pc(0),
333 translateDelta(0), accessDelta(0), depth(0)
334 {
335 setPhys(paddr, size, flags, mid, curTick());
336 }
337
338 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
339 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
340 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
341 _extraData(0), _contextId(0), _threadId(0), _pc(0),
342 translateDelta(0), accessDelta(0), depth(0)
343 {
344 setPhys(paddr, size, flags, mid, time);
345 }
346
347 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
348 Addr pc)
349 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
350 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
351 _extraData(0), _contextId(0), _threadId(0), _pc(0),
352 translateDelta(0), accessDelta(0), depth(0)
353 {
354 setPhys(paddr, size, flags, mid, time);
355 privateFlags.set(VALID_PC);
356 _pc = pc;
357 }
358
359 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
360 Addr pc, int cid, ThreadID tid)
361 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
362 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
363 _extraData(0), _contextId(0), _threadId(0), _pc(0),
364 translateDelta(0), accessDelta(0), depth(0)
365 {
366 setVirt(asid, vaddr, size, flags, mid, pc);
367 setThreadContext(cid, tid);
368 }
369
370 ~Request() {}
371
372 /**
373 * Set up CPU and thread numbers.
374 */
375 void
376 setThreadContext(int context_id, ThreadID tid)
377 {
378 _contextId = context_id;
379 _threadId = tid;
380 privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
381 }
382
383 /**
384 * Set up a virtual (e.g., CPU) request in a previously
385 * allocated Request object.
386 */
387 void
388 setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
389 Addr pc)
390 {
391 _asid = asid;
392 _vaddr = vaddr;
393 _size = size;
394 _masterId = mid;
395 _pc = pc;
396 _time = curTick();
397
398 _flags.clear(~STICKY_FLAGS);
399 _flags.set(flags);
400 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
401 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
402 depth = 0;
403 accessDelta = 0;
404 translateDelta = 0;
405 }
406
407 /**
408 * Set just the physical address. This usually used to record the
409 * result of a translation. However, when using virtualized CPUs
410 * setPhys() is sometimes called to finalize a physical address
411 * without a virtual address, so we can't check if the virtual
412 * address is valid.
413 */
414 void
415 setPaddr(Addr paddr)
416 {
417 _paddr = paddr;
418 privateFlags.set(VALID_PADDR);
419 }
420
421 /**
422 * Generate two requests as if this request had been split into two
423 * pieces. The original request can't have been translated already.
424 */
425 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
426 {
427 assert(privateFlags.isSet(VALID_VADDR));
428 assert(privateFlags.noneSet(VALID_PADDR));
429 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
430 req1 = new Request(*this);
431 req2 = new Request(*this);
432 req1->_size = split_addr - _vaddr;
433 req2->_vaddr = split_addr;
434 req2->_size = _size - req1->_size;
435 }
436
437 /**
438 * Accessor for paddr.
439 */
440 bool
441 hasPaddr() const
442 {
443 return privateFlags.isSet(VALID_PADDR);
444 }
445
446 Addr
447 getPaddr() const
448 {
449 assert(privateFlags.isSet(VALID_PADDR));
450 return _paddr;
451 }
452
453 /**
454 * Time for the TLB/table walker to successfully translate this request.
455 */
456 Tick translateDelta;
457
458 /**
459 * Access latency to complete this memory transaction not including
460 * translation time.
461 */
462 Tick accessDelta;
463
464 /**
465 * Level of the cache hierachy where this request was responded to
466 * (e.g. 0 = L1; 1 = L2).
467 */
468 mutable int depth;
469
470 /**
471 * Accessor for size.
472 */
473 bool
474 hasSize() const
475 {
476 return privateFlags.isSet(VALID_SIZE);
477 }
478
479 unsigned
480 getSize() const
481 {
482 assert(privateFlags.isSet(VALID_SIZE));
483 return _size;
484 }
485
486 /** Accessor for time. */
487 Tick
488 time() const
489 {
490 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
491 return _time;
492 }
493
494 /** Accessor for flags. */
495 Flags
496 getFlags()
497 {
498 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
499 return _flags;
500 }
501
502 /** Note that unlike other accessors, this function sets *specific
503 flags* (ORs them in); it does not assign its argument to the
504 _flags field. Thus this method should rightly be called
505 setFlags() and not just flags(). */
506 void
507 setFlags(Flags flags)
508 {
509 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
510 _flags.set(flags);
511 }
512
513 /** Accessor function for vaddr.*/
514 bool
515 hasVaddr() const
516 {
517 return privateFlags.isSet(VALID_VADDR);
518 }
519
520 Addr
521 getVaddr() const
522 {
523 assert(privateFlags.isSet(VALID_VADDR));
524 return _vaddr;
525 }
526
527 /** Accesssor for the requestor id. */
528 MasterID
529 masterId() const
530 {
531 return _masterId;
532 }
533
534 uint32_t
535 taskId() const
536 {
537 return _taskId;
538 }
539
540 void
541 taskId(uint32_t id) {
542 _taskId = id;
543 }
544
545 /** Accessor function for asid.*/
546 int
547 getAsid() const
548 {
549 assert(privateFlags.isSet(VALID_VADDR));
550 return _asid;
551 }
552
553 /** Accessor function for asid.*/
554 void
555 setAsid(int asid)
556 {
557 _asid = asid;
558 }
559
560 /** Accessor function for architecture-specific flags.*/
561 ArchFlagsType
562 getArchFlags() const
563 {
564 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
565 return _flags & ARCH_BITS;
566 }
567
568 /** Accessor function to check if sc result is valid. */
569 bool
570 extraDataValid() const
571 {
572 return privateFlags.isSet(VALID_EXTRA_DATA);
573 }
574
575 /** Accessor function for store conditional return value.*/
576 uint64_t
577 getExtraData() const
578 {
579 assert(privateFlags.isSet(VALID_EXTRA_DATA));
580 return _extraData;
581 }
582
583 /** Accessor function for store conditional return value.*/
584 void
585 setExtraData(uint64_t extraData)
586 {
587 _extraData = extraData;
588 privateFlags.set(VALID_EXTRA_DATA);
589 }
590
591 bool
592 hasContextId() const
593 {
594 return privateFlags.isSet(VALID_CONTEXT_ID);
595 }
596
597 /** Accessor function for context ID.*/
598 int
599 contextId() const
600 {
601 assert(privateFlags.isSet(VALID_CONTEXT_ID));
602 return _contextId;
603 }
604
605 /** Accessor function for thread ID. */
606 ThreadID
607 threadId() const
608 {
609 assert(privateFlags.isSet(VALID_THREAD_ID));
610 return _threadId;
611 }
612
613 void
614 setPC(Addr pc)
615 {
616 privateFlags.set(VALID_PC);
617 _pc = pc;
618 }
619
620 bool
621 hasPC() const
622 {
623 return privateFlags.isSet(VALID_PC);
624 }
625
626 /** Accessor function for pc.*/
627 Addr
628 getPC() const
629 {
630 assert(privateFlags.isSet(VALID_PC));
631 return _pc;
632 }
633
634 /**
635 * Increment/Get the depth at which this request is responded to.
636 * This currently happens when the request misses in any cache level.
637 */
638 void incAccessDepth() const { depth++; }
639 int getAccessDepth() const { return depth; }
640
641 /**
642 * Set/Get the time taken for this request to be successfully translated.
643 */
644 void setTranslateLatency() { translateDelta = curTick() - _time; }
645 Tick getTranslateLatency() const { return translateDelta; }
646
647 /**
648 * Set/Get the time taken to complete this request's access, not including
649 * the time to successfully translate the request.
650 */
651 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
652 Tick getAccessLatency() const { return accessDelta; }
653
654 /** Accessor functions for flags. Note that these are for testing
655 only; setting flags should be done via setFlags(). */
656 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
657 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
658 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
659 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
660 bool isLLSC() const { return _flags.isSet(LLSC); }
661 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
662 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
|
| 663 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
664 bool isRelease() const { return _flags.isSet(RELEASE); }
665 bool isAcquireRelease() const {
666 return _flags.isSet(RELEASE | ACQUIRE);
667 }
|
658 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
659 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
660 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
661 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
662 bool isSecure() const { return _flags.isSet(SECURE); }
663 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
| 668 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
669 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
670 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
671 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
672 bool isSecure() const { return _flags.isSet(SECURE); }
673 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
|
| 674 void setAcquire() { _flags.set(ACQUIRE); }
675 void setRelease() { _flags.set(RELEASE); }
|
664};
665
666#endif // __MEM_REQUEST_HH__
| 676};
677
678#endif // __MEM_REQUEST_HH__
|