1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 * Ali Saidi
43 */
44
45/**
46 * @file
47 * Declaration of a request, the overall memory request consisting of
48 the parts of the request that are persistent throughout the transaction.
49 */
50
51#ifndef __MEM_REQUEST_HH__
52#define __MEM_REQUEST_HH__
53
54#include <cassert>
55#include <climits>
56
57#include "base/flags.hh"
58#include "base/misc.hh"
59#include "base/types.hh"
60#include "sim/core.hh"
61
62/**
63 * Special TaskIds that are used for per-context-switch stats dumps
64 * and Cache Occupancy. Having too many tasks seems to be a problem
65 * with vector stats. 1024 seems to be a reasonable number that
66 * doesn't cause a problem with stats and is large enough to realistic
67 * benchmarks (Linux/Android boot, BBench, etc.)
68 */
69
70namespace ContextSwitchTaskId {
71 enum TaskId {
72 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
73 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
74 DMA = 1023, /* Mostly Table Walker */
75 Unknown = 1024,
76 NumTaskId
77 };
78}
79
80class Request;
81
82typedef Request* RequestPtr;
83typedef uint16_t MasterID;
84
85class Request
86{
87 public:
88 typedef uint32_t FlagsType;
89 typedef uint8_t ArchFlagsType;
90 typedef ::Flags<FlagsType> Flags;
91
92 /**
93 * Architecture specific flags.
94 *
95 * These bits int the flag field are reserved for
96 * architecture-specific code. For example, SPARC uses them to
97 * represent ASIs.
98 */
99 static const FlagsType ARCH_BITS = 0x000000FF;
100 /** The request was an instruction fetch. */
101 static const FlagsType INST_FETCH = 0x00000100;
102 /** The virtual address is also the physical address. */
103 static const FlagsType PHYSICAL = 0x00000200;
104 /** The request is an ALPHA VPTE pal access (hw_ld). */
105 static const FlagsType VPTE = 0x00000400;
106 /** Use the alternate mode bits in ALPHA. */
107 static const FlagsType ALTMODE = 0x00000800;
108 /** The request is to an uncacheable address. */
109 static const FlagsType UNCACHEABLE = 0x00001000;
110 /** This request is to a memory mapped register. */
111 static const FlagsType MMAPPED_IPR = 0x00002000;
112 /** This request is a clear exclusive. */
113 static const FlagsType CLEAR_LL = 0x00004000;
114 /** This request is made in privileged mode. */
115 static const FlagsType PRIVILEGED = 0x00008000;
116
117 /** This is a write that is targeted and zeroing an entire cache block.
118 * There is no need for a read/modify/write
119 */
120 static const FlagsType CACHE_BLOCK_ZERO = 0x00010000;
121
122 /** The request should not cause a memory access. */
123 static const FlagsType NO_ACCESS = 0x00080000;
124 /** This request will lock or unlock the accessed memory. When used with
125 * a load, the access locks the particular chunk of memory. When used
126 * with a store, it unlocks. The rule is that locked accesses have to be
127 * made up of a locked load, some operation on the data, and then a locked
128 * store.
129 */
130 static const FlagsType LOCKED = 0x00100000;
131 /** The request is a Load locked/store conditional. */
132 static const FlagsType LLSC = 0x00200000;
133 /** This request is for a memory swap. */
134 static const FlagsType MEM_SWAP = 0x00400000;
135 static const FlagsType MEM_SWAP_COND = 0x00800000;
136
137 /** The request is a prefetch. */
138 static const FlagsType PREFETCH = 0x01000000;
139 /** The request should be prefetched into the exclusive state. */
140 static const FlagsType PF_EXCLUSIVE = 0x02000000;
141 /** The request should be marked as LRU. */
142 static const FlagsType EVICT_NEXT = 0x04000000;
143
144 /** The request should be handled by the generic IPR code (only
145 * valid together with MMAPPED_IPR) */
146 static const FlagsType GENERIC_IPR = 0x08000000;
147
148 /** The request targets the secure memory space. */
149 static const FlagsType SECURE = 0x10000000;
150 /** The request is a page table walk */
151 static const FlagsType PT_WALK = 0x20000000;
152
153 /** These flags are *not* cleared when a Request object is reused
154 (assigned a new address). */
155 static const FlagsType STICKY_FLAGS = INST_FETCH;
156
157 /** Request Ids that are statically allocated
158 * @{*/
159 /** This request id is used for writeback requests by the caches */
160 static const MasterID wbMasterId = 0;
161 /** This request id is used for functional requests that don't come from a
162 * particular device
163 */
164 static const MasterID funcMasterId = 1;
165 /** This request id is used for message signaled interrupts */
166 static const MasterID intMasterId = 2;
167 /** Invalid request id for assertion checking only. It is invalid behavior
168 * to ever send this id as part of a request.
169 * @todo C++1x replace with numeric_limits when constexpr is added */
170 static const MasterID invldMasterId = USHRT_MAX;
171 /** @} */
172
173 /** Invalid or unknown Pid. Possible when operating system is not present
174 * or has not assigned a pid yet */
175 static const uint32_t invldPid = UINT_MAX;
176
177 private:
178 typedef uint8_t PrivateFlagsType;
179 typedef ::Flags<PrivateFlagsType> PrivateFlags;
180
181 /** Whether or not the size is valid. */
182 static const PrivateFlagsType VALID_SIZE = 0x00000001;
183 /** Whether or not paddr is valid (has been written yet). */
184 static const PrivateFlagsType VALID_PADDR = 0x00000002;
185 /** Whether or not the vaddr & asid are valid. */
186 static const PrivateFlagsType VALID_VADDR = 0x00000004;
187 /** Whether or not the pc is valid. */
188 static const PrivateFlagsType VALID_PC = 0x00000010;
189 /** Whether or not the context ID is valid. */
190 static const PrivateFlagsType VALID_CONTEXT_ID = 0x00000020;
191 static const PrivateFlagsType VALID_THREAD_ID = 0x00000040;
192 /** Whether or not the sc result is valid. */
193 static const PrivateFlagsType VALID_EXTRA_DATA = 0x00000080;
194
195 /** These flags are *not* cleared when a Request object is reused
196 (assigned a new address). */
197 static const PrivateFlagsType STICKY_PRIVATE_FLAGS =
198 VALID_CONTEXT_ID | VALID_THREAD_ID;
199
200 private:
201 /**
202 * The physical address of the request. Valid only if validPaddr
203 * is set.
204 */
205 Addr _paddr;
206
207 /**
208 * The size of the request. This field must be set when vaddr or
209 * paddr is written via setVirt() or setPhys(), so it is always
210 * valid as long as one of the address fields is valid.
211 */
212 int _size;
213
214 /** The requestor ID which is unique in the system for all ports
215 * that are capable of issuing a transaction
216 */
217 MasterID _masterId;
218
219 /** Flag structure for the request. */
220 Flags _flags;
221
222 /** Private flags for field validity checking. */
223 PrivateFlags privateFlags;
224
225 /**
226 * The time this request was started. Used to calculate
227 * latencies. This field is set to curTick() any time paddr or vaddr
228 * is written.
229 */
230 Tick _time;
231
232 /**
233 * The task id associated with this request
234 */
235 uint32_t _taskId;
236
237 /** The address space ID. */
238 int _asid;
239
240 /** The virtual address of the request. */
241 Addr _vaddr;
242
243 /**
244 * Extra data for the request, such as the return value of
245 * store conditional or the compare value for a CAS. */
246 uint64_t _extraData;
247
248 /** The context ID (for statistics, typically). */
249 int _contextId;
250 /** The thread ID (id within this CPU) */
251 int _threadId;
252
253 /** program counter of initiating access; for tracing/debugging */
254 Addr _pc;
255
256 public:
257 /** Minimal constructor. No fields are initialized.
258 * (Note that _flags and privateFlags are cleared by Flags
259 * default constructor.)
260 */
261 Request()
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 * Ali Saidi
43 */
44
45/**
46 * @file
47 * Declaration of a request, the overall memory request consisting of
48 the parts of the request that are persistent throughout the transaction.
49 */
50
51#ifndef __MEM_REQUEST_HH__
52#define __MEM_REQUEST_HH__
53
54#include <cassert>
55#include <climits>
56
57#include "base/flags.hh"
58#include "base/misc.hh"
59#include "base/types.hh"
60#include "sim/core.hh"
61
62/**
63 * Special TaskIds that are used for per-context-switch stats dumps
64 * and Cache Occupancy. Having too many tasks seems to be a problem
65 * with vector stats. 1024 seems to be a reasonable number that
66 * doesn't cause a problem with stats and is large enough to realistic
67 * benchmarks (Linux/Android boot, BBench, etc.)
68 */
69
70namespace ContextSwitchTaskId {
71 enum TaskId {
72 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
73 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
74 DMA = 1023, /* Mostly Table Walker */
75 Unknown = 1024,
76 NumTaskId
77 };
78}
79
80class Request;
81
82typedef Request* RequestPtr;
83typedef uint16_t MasterID;
84
85class Request
86{
87 public:
88 typedef uint32_t FlagsType;
89 typedef uint8_t ArchFlagsType;
90 typedef ::Flags<FlagsType> Flags;
91
92 /**
93 * Architecture specific flags.
94 *
95 * These bits int the flag field are reserved for
96 * architecture-specific code. For example, SPARC uses them to
97 * represent ASIs.
98 */
99 static const FlagsType ARCH_BITS = 0x000000FF;
100 /** The request was an instruction fetch. */
101 static const FlagsType INST_FETCH = 0x00000100;
102 /** The virtual address is also the physical address. */
103 static const FlagsType PHYSICAL = 0x00000200;
104 /** The request is an ALPHA VPTE pal access (hw_ld). */
105 static const FlagsType VPTE = 0x00000400;
106 /** Use the alternate mode bits in ALPHA. */
107 static const FlagsType ALTMODE = 0x00000800;
108 /** The request is to an uncacheable address. */
109 static const FlagsType UNCACHEABLE = 0x00001000;
110 /** This request is to a memory mapped register. */
111 static const FlagsType MMAPPED_IPR = 0x00002000;
112 /** This request is a clear exclusive. */
113 static const FlagsType CLEAR_LL = 0x00004000;
114 /** This request is made in privileged mode. */
115 static const FlagsType PRIVILEGED = 0x00008000;
116
117 /** This is a write that is targeted and zeroing an entire cache block.
118 * There is no need for a read/modify/write
119 */
120 static const FlagsType CACHE_BLOCK_ZERO = 0x00010000;
121
122 /** The request should not cause a memory access. */
123 static const FlagsType NO_ACCESS = 0x00080000;
124 /** This request will lock or unlock the accessed memory. When used with
125 * a load, the access locks the particular chunk of memory. When used
126 * with a store, it unlocks. The rule is that locked accesses have to be
127 * made up of a locked load, some operation on the data, and then a locked
128 * store.
129 */
130 static const FlagsType LOCKED = 0x00100000;
131 /** The request is a Load locked/store conditional. */
132 static const FlagsType LLSC = 0x00200000;
133 /** This request is for a memory swap. */
134 static const FlagsType MEM_SWAP = 0x00400000;
135 static const FlagsType MEM_SWAP_COND = 0x00800000;
136
137 /** The request is a prefetch. */
138 static const FlagsType PREFETCH = 0x01000000;
139 /** The request should be prefetched into the exclusive state. */
140 static const FlagsType PF_EXCLUSIVE = 0x02000000;
141 /** The request should be marked as LRU. */
142 static const FlagsType EVICT_NEXT = 0x04000000;
143
144 /** The request should be handled by the generic IPR code (only
145 * valid together with MMAPPED_IPR) */
146 static const FlagsType GENERIC_IPR = 0x08000000;
147
148 /** The request targets the secure memory space. */
149 static const FlagsType SECURE = 0x10000000;
150 /** The request is a page table walk */
151 static const FlagsType PT_WALK = 0x20000000;
152
153 /** These flags are *not* cleared when a Request object is reused
154 (assigned a new address). */
155 static const FlagsType STICKY_FLAGS = INST_FETCH;
156
157 /** Request Ids that are statically allocated
158 * @{*/
159 /** This request id is used for writeback requests by the caches */
160 static const MasterID wbMasterId = 0;
161 /** This request id is used for functional requests that don't come from a
162 * particular device
163 */
164 static const MasterID funcMasterId = 1;
165 /** This request id is used for message signaled interrupts */
166 static const MasterID intMasterId = 2;
167 /** Invalid request id for assertion checking only. It is invalid behavior
168 * to ever send this id as part of a request.
169 * @todo C++1x replace with numeric_limits when constexpr is added */
170 static const MasterID invldMasterId = USHRT_MAX;
171 /** @} */
172
173 /** Invalid or unknown Pid. Possible when operating system is not present
174 * or has not assigned a pid yet */
175 static const uint32_t invldPid = UINT_MAX;
176
177 private:
178 typedef uint8_t PrivateFlagsType;
179 typedef ::Flags<PrivateFlagsType> PrivateFlags;
180
181 /** Whether or not the size is valid. */
182 static const PrivateFlagsType VALID_SIZE = 0x00000001;
183 /** Whether or not paddr is valid (has been written yet). */
184 static const PrivateFlagsType VALID_PADDR = 0x00000002;
185 /** Whether or not the vaddr & asid are valid. */
186 static const PrivateFlagsType VALID_VADDR = 0x00000004;
187 /** Whether or not the pc is valid. */
188 static const PrivateFlagsType VALID_PC = 0x00000010;
189 /** Whether or not the context ID is valid. */
190 static const PrivateFlagsType VALID_CONTEXT_ID = 0x00000020;
191 static const PrivateFlagsType VALID_THREAD_ID = 0x00000040;
192 /** Whether or not the sc result is valid. */
193 static const PrivateFlagsType VALID_EXTRA_DATA = 0x00000080;
194
195 /** These flags are *not* cleared when a Request object is reused
196 (assigned a new address). */
197 static const PrivateFlagsType STICKY_PRIVATE_FLAGS =
198 VALID_CONTEXT_ID | VALID_THREAD_ID;
199
200 private:
201 /**
202 * The physical address of the request. Valid only if validPaddr
203 * is set.
204 */
205 Addr _paddr;
206
207 /**
208 * The size of the request. This field must be set when vaddr or
209 * paddr is written via setVirt() or setPhys(), so it is always
210 * valid as long as one of the address fields is valid.
211 */
212 int _size;
213
214 /** The requestor ID which is unique in the system for all ports
215 * that are capable of issuing a transaction
216 */
217 MasterID _masterId;
218
219 /** Flag structure for the request. */
220 Flags _flags;
221
222 /** Private flags for field validity checking. */
223 PrivateFlags privateFlags;
224
225 /**
226 * The time this request was started. Used to calculate
227 * latencies. This field is set to curTick() any time paddr or vaddr
228 * is written.
229 */
230 Tick _time;
231
232 /**
233 * The task id associated with this request
234 */
235 uint32_t _taskId;
236
237 /** The address space ID. */
238 int _asid;
239
240 /** The virtual address of the request. */
241 Addr _vaddr;
242
243 /**
244 * Extra data for the request, such as the return value of
245 * store conditional or the compare value for a CAS. */
246 uint64_t _extraData;
247
248 /** The context ID (for statistics, typically). */
249 int _contextId;
250 /** The thread ID (id within this CPU) */
251 int _threadId;
252
253 /** program counter of initiating access; for tracing/debugging */
254 Addr _pc;
255
256 public:
257 /** Minimal constructor. No fields are initialized.
258 * (Note that _flags and privateFlags are cleared by Flags
259 * default constructor.)
260 */
261 Request()
|
262 : _taskId(ContextSwitchTaskId::Unknown),
263 translateDelta(0), accessDelta(0), depth(0)
| 262 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
263 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
264 _extraData(0), _contextId(0), _threadId(0), _pc(0),
265 translateDelta(0), accessDelta(0), depth(0)
|
264 {}
265
266 /**
267 * Constructor for physical (e.g. device) requests. Initializes
268 * just physical address, size, flags, and timestamp (to curTick()).
269 * These fields are adequate to perform a request.
270 */
271 Request(Addr paddr, int size, Flags flags, MasterID mid)
| 266 {}
267
268 /**
269 * Constructor for physical (e.g. device) requests. Initializes
270 * just physical address, size, flags, and timestamp (to curTick()).
271 * These fields are adequate to perform a request.
272 */
273 Request(Addr paddr, int size, Flags flags, MasterID mid)
|
272 : _taskId(ContextSwitchTaskId::Unknown)
| 274 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
275 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
276 _extraData(0), _contextId(0), _threadId(0), _pc(0),
277 translateDelta(0), accessDelta(0), depth(0)
|
273 {
274 setPhys(paddr, size, flags, mid);
275 }
276
277 Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
| 278 {
279 setPhys(paddr, size, flags, mid);
280 }
281
282 Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
|
278 : _taskId(ContextSwitchTaskId::Unknown)
| 283 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
284 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
285 _extraData(0), _contextId(0), _threadId(0), _pc(0),
286 translateDelta(0), accessDelta(0), depth(0)
|
279 {
280 setPhys(paddr, size, flags, mid, time);
281 }
282
283 Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time, Addr pc)
| 287 {
288 setPhys(paddr, size, flags, mid, time);
289 }
290
291 Request(Addr paddr, int size, Flags flags, MasterID mid, Tick time, Addr pc)
|
284 : _taskId(ContextSwitchTaskId::Unknown)
| 292 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
293 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
294 _extraData(0), _contextId(0), _threadId(0), _pc(0),
295 translateDelta(0), accessDelta(0), depth(0)
|
285 {
286 setPhys(paddr, size, flags, mid, time);
287 privateFlags.set(VALID_PC);
288 _pc = pc;
289 }
290
291 Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
292 int cid, ThreadID tid)
| 296 {
297 setPhys(paddr, size, flags, mid, time);
298 privateFlags.set(VALID_PC);
299 _pc = pc;
300 }
301
302 Request(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc,
303 int cid, ThreadID tid)
|
293 : _taskId(ContextSwitchTaskId::Unknown)
| 304 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
305 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
306 _extraData(0), _contextId(0), _threadId(0), _pc(0),
307 translateDelta(0), accessDelta(0), depth(0)
|
294 {
295 setVirt(asid, vaddr, size, flags, mid, pc);
296 setThreadContext(cid, tid);
297 }
298
299 ~Request() {}
300
301 /**
302 * Set up CPU and thread numbers.
303 */
304 void
305 setThreadContext(int context_id, ThreadID tid)
306 {
307 _contextId = context_id;
308 _threadId = tid;
309 privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
310 }
311
312 /**
313 * Set up a physical (e.g. device) request in a previously
314 * allocated Request object.
315 */
316 void
317 setPhys(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
318 {
319 assert(size >= 0);
320 _paddr = paddr;
321 _size = size;
322 _time = time;
323 _masterId = mid;
324 _flags.clear(~STICKY_FLAGS);
325 _flags.set(flags);
326 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
327 privateFlags.set(VALID_PADDR|VALID_SIZE);
328 depth = 0;
329 accessDelta = 0;
330 //translateDelta = 0;
331 }
332
333 void
334 setPhys(Addr paddr, int size, Flags flags, MasterID mid)
335 {
336 setPhys(paddr, size, flags, mid, curTick());
337 }
338
339 /**
340 * Set up a virtual (e.g., CPU) request in a previously
341 * allocated Request object.
342 */
343 void
344 setVirt(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc)
345 {
346 assert(size >= 0);
347 _asid = asid;
348 _vaddr = vaddr;
349 _size = size;
350 _masterId = mid;
351 _pc = pc;
352 _time = curTick();
353
354 _flags.clear(~STICKY_FLAGS);
355 _flags.set(flags);
356 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
357 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
358 depth = 0;
359 accessDelta = 0;
360 translateDelta = 0;
361 }
362
363 /**
364 * Set just the physical address. This usually used to record the
365 * result of a translation. However, when using virtualized CPUs
366 * setPhys() is sometimes called to finalize a physical address
367 * without a virtual address, so we can't check if the virtual
368 * address is valid.
369 */
370 void
371 setPaddr(Addr paddr)
372 {
373 _paddr = paddr;
374 privateFlags.set(VALID_PADDR);
375 }
376
377 /**
378 * Generate two requests as if this request had been split into two
379 * pieces. The original request can't have been translated already.
380 */
381 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
382 {
383 assert(privateFlags.isSet(VALID_VADDR));
384 assert(privateFlags.noneSet(VALID_PADDR));
385 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
386 req1 = new Request;
387 *req1 = *this;
388 req2 = new Request;
389 *req2 = *this;
390 req1->_size = split_addr - _vaddr;
391 req2->_vaddr = split_addr;
392 req2->_size = _size - req1->_size;
393 }
394
395 /**
396 * Accessor for paddr.
397 */
398 bool
399 hasPaddr()
400 {
401 return privateFlags.isSet(VALID_PADDR);
402 }
403
404 Addr
405 getPaddr()
406 {
407 assert(privateFlags.isSet(VALID_PADDR));
408 return _paddr;
409 }
410
411 /**
412 * Time for the TLB/table walker to successfully translate this request.
413 */
414 Tick translateDelta;
415
416 /**
417 * Access latency to complete this memory transaction not including
418 * translation time.
419 */
420 Tick accessDelta;
421
422 /**
423 * Level of the cache hierachy where this request was responded to
424 * (e.g. 0 = L1; 1 = L2).
425 */
426 int depth;
427
428 /**
429 * Accessor for size.
430 */
431 bool
432 hasSize()
433 {
434 return privateFlags.isSet(VALID_SIZE);
435 }
436
437 int
438 getSize()
439 {
440 assert(privateFlags.isSet(VALID_SIZE));
441 return _size;
442 }
443
444 /** Accessor for time. */
445 Tick
446 time() const
447 {
448 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
449 return _time;
450 }
451
452 void
453 time(Tick time)
454 {
455 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
456 _time = time;
457 }
458
459 /** Accessor for flags. */
460 Flags
461 getFlags()
462 {
463 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
464 return _flags;
465 }
466
467 /** Note that unlike other accessors, this function sets *specific
468 flags* (ORs them in); it does not assign its argument to the
469 _flags field. Thus this method should rightly be called
470 setFlags() and not just flags(). */
471 void
472 setFlags(Flags flags)
473 {
474 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
475 _flags.set(flags);
476 }
477
478 void
479 setArchFlags(Flags flags)
480 {
481 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
482 _flags.set(flags & ARCH_BITS);
483 }
484
485 /** Accessor function for vaddr.*/
486 Addr
487 getVaddr()
488 {
489 assert(privateFlags.isSet(VALID_VADDR));
490 return _vaddr;
491 }
492
493 /** Accesssor for the requestor id. */
494 MasterID
495 masterId()
496 {
497 return _masterId;
498 }
499
500 uint32_t
501 taskId() const
502 {
503 return _taskId;
504 }
505
506 void
507 taskId(uint32_t id) {
508 _taskId = id;
509 }
510
511 /** Accessor function for asid.*/
512 int
513 getAsid()
514 {
515 assert(privateFlags.isSet(VALID_VADDR));
516 return _asid;
517 }
518
519 /** Accessor function for asid.*/
520 void
521 setAsid(int asid)
522 {
523 _asid = asid;
524 }
525
526 /** Accessor function for architecture-specific flags.*/
527 ArchFlagsType
528 getArchFlags()
529 {
530 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
531 return _flags & ARCH_BITS;
532 }
533
534 /** Accessor function to check if sc result is valid. */
535 bool
536 extraDataValid()
537 {
538 return privateFlags.isSet(VALID_EXTRA_DATA);
539 }
540
541 /** Accessor function for store conditional return value.*/
542 uint64_t
543 getExtraData() const
544 {
545 assert(privateFlags.isSet(VALID_EXTRA_DATA));
546 return _extraData;
547 }
548
549 /** Accessor function for store conditional return value.*/
550 void
551 setExtraData(uint64_t extraData)
552 {
553 _extraData = extraData;
554 privateFlags.set(VALID_EXTRA_DATA);
555 }
556
557 bool
558 hasContextId() const
559 {
560 return privateFlags.isSet(VALID_CONTEXT_ID);
561 }
562
563 /** Accessor function for context ID.*/
564 int
565 contextId() const
566 {
567 assert(privateFlags.isSet(VALID_CONTEXT_ID));
568 return _contextId;
569 }
570
571 /** Accessor function for thread ID. */
572 int
573 threadId() const
574 {
575 assert(privateFlags.isSet(VALID_THREAD_ID));
576 return _threadId;
577 }
578
579 void
580 setPC(Addr pc)
581 {
582 privateFlags.set(VALID_PC);
583 _pc = pc;
584 }
585
586 bool
587 hasPC() const
588 {
589 return privateFlags.isSet(VALID_PC);
590 }
591
592 /** Accessor function for pc.*/
593 Addr
594 getPC() const
595 {
596 assert(privateFlags.isSet(VALID_PC));
597 return _pc;
598 }
599
600 /**
601 * Increment/Get the depth at which this request is responded to.
602 * This currently happens when the request misses in any cache level.
603 */
604 void incAccessDepth() { depth++; }
605 int getAccessDepth() const { return depth; }
606
607 /**
608 * Set/Get the time taken for this request to be successfully translated.
609 */
610 void setTranslateLatency() { translateDelta = curTick() - _time; }
611 Tick getTranslateLatency() const { return translateDelta; }
612
613 /**
614 * Set/Get the time taken to complete this request's access, not including
615 * the time to successfully translate the request.
616 */
617 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
618 Tick getAccessLatency() const { return accessDelta; }
619
620 /** Accessor functions for flags. Note that these are for testing
621 only; setting flags should be done via setFlags(). */
622 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
623 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
624 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
625 bool isLLSC() const { return _flags.isSet(LLSC); }
626 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
627 bool isLocked() const { return _flags.isSet(LOCKED); }
628 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
629 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
630 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
631 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
632 bool isSecure() const { return _flags.isSet(SECURE); }
633 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
634};
635
636#endif // __MEM_REQUEST_HH__
| 308 {
309 setVirt(asid, vaddr, size, flags, mid, pc);
310 setThreadContext(cid, tid);
311 }
312
313 ~Request() {}
314
315 /**
316 * Set up CPU and thread numbers.
317 */
318 void
319 setThreadContext(int context_id, ThreadID tid)
320 {
321 _contextId = context_id;
322 _threadId = tid;
323 privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
324 }
325
326 /**
327 * Set up a physical (e.g. device) request in a previously
328 * allocated Request object.
329 */
330 void
331 setPhys(Addr paddr, int size, Flags flags, MasterID mid, Tick time)
332 {
333 assert(size >= 0);
334 _paddr = paddr;
335 _size = size;
336 _time = time;
337 _masterId = mid;
338 _flags.clear(~STICKY_FLAGS);
339 _flags.set(flags);
340 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
341 privateFlags.set(VALID_PADDR|VALID_SIZE);
342 depth = 0;
343 accessDelta = 0;
344 //translateDelta = 0;
345 }
346
347 void
348 setPhys(Addr paddr, int size, Flags flags, MasterID mid)
349 {
350 setPhys(paddr, size, flags, mid, curTick());
351 }
352
353 /**
354 * Set up a virtual (e.g., CPU) request in a previously
355 * allocated Request object.
356 */
357 void
358 setVirt(int asid, Addr vaddr, int size, Flags flags, MasterID mid, Addr pc)
359 {
360 assert(size >= 0);
361 _asid = asid;
362 _vaddr = vaddr;
363 _size = size;
364 _masterId = mid;
365 _pc = pc;
366 _time = curTick();
367
368 _flags.clear(~STICKY_FLAGS);
369 _flags.set(flags);
370 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
371 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
372 depth = 0;
373 accessDelta = 0;
374 translateDelta = 0;
375 }
376
377 /**
378 * Set just the physical address. This usually used to record the
379 * result of a translation. However, when using virtualized CPUs
380 * setPhys() is sometimes called to finalize a physical address
381 * without a virtual address, so we can't check if the virtual
382 * address is valid.
383 */
384 void
385 setPaddr(Addr paddr)
386 {
387 _paddr = paddr;
388 privateFlags.set(VALID_PADDR);
389 }
390
391 /**
392 * Generate two requests as if this request had been split into two
393 * pieces. The original request can't have been translated already.
394 */
395 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
396 {
397 assert(privateFlags.isSet(VALID_VADDR));
398 assert(privateFlags.noneSet(VALID_PADDR));
399 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
400 req1 = new Request;
401 *req1 = *this;
402 req2 = new Request;
403 *req2 = *this;
404 req1->_size = split_addr - _vaddr;
405 req2->_vaddr = split_addr;
406 req2->_size = _size - req1->_size;
407 }
408
409 /**
410 * Accessor for paddr.
411 */
412 bool
413 hasPaddr()
414 {
415 return privateFlags.isSet(VALID_PADDR);
416 }
417
418 Addr
419 getPaddr()
420 {
421 assert(privateFlags.isSet(VALID_PADDR));
422 return _paddr;
423 }
424
425 /**
426 * Time for the TLB/table walker to successfully translate this request.
427 */
428 Tick translateDelta;
429
430 /**
431 * Access latency to complete this memory transaction not including
432 * translation time.
433 */
434 Tick accessDelta;
435
436 /**
437 * Level of the cache hierachy where this request was responded to
438 * (e.g. 0 = L1; 1 = L2).
439 */
440 int depth;
441
442 /**
443 * Accessor for size.
444 */
445 bool
446 hasSize()
447 {
448 return privateFlags.isSet(VALID_SIZE);
449 }
450
451 int
452 getSize()
453 {
454 assert(privateFlags.isSet(VALID_SIZE));
455 return _size;
456 }
457
458 /** Accessor for time. */
459 Tick
460 time() const
461 {
462 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
463 return _time;
464 }
465
466 void
467 time(Tick time)
468 {
469 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
470 _time = time;
471 }
472
473 /** Accessor for flags. */
474 Flags
475 getFlags()
476 {
477 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
478 return _flags;
479 }
480
481 /** Note that unlike other accessors, this function sets *specific
482 flags* (ORs them in); it does not assign its argument to the
483 _flags field. Thus this method should rightly be called
484 setFlags() and not just flags(). */
485 void
486 setFlags(Flags flags)
487 {
488 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
489 _flags.set(flags);
490 }
491
492 void
493 setArchFlags(Flags flags)
494 {
495 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
496 _flags.set(flags & ARCH_BITS);
497 }
498
499 /** Accessor function for vaddr.*/
500 Addr
501 getVaddr()
502 {
503 assert(privateFlags.isSet(VALID_VADDR));
504 return _vaddr;
505 }
506
507 /** Accesssor for the requestor id. */
508 MasterID
509 masterId()
510 {
511 return _masterId;
512 }
513
514 uint32_t
515 taskId() const
516 {
517 return _taskId;
518 }
519
520 void
521 taskId(uint32_t id) {
522 _taskId = id;
523 }
524
525 /** Accessor function for asid.*/
526 int
527 getAsid()
528 {
529 assert(privateFlags.isSet(VALID_VADDR));
530 return _asid;
531 }
532
533 /** Accessor function for asid.*/
534 void
535 setAsid(int asid)
536 {
537 _asid = asid;
538 }
539
540 /** Accessor function for architecture-specific flags.*/
541 ArchFlagsType
542 getArchFlags()
543 {
544 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
545 return _flags & ARCH_BITS;
546 }
547
548 /** Accessor function to check if sc result is valid. */
549 bool
550 extraDataValid()
551 {
552 return privateFlags.isSet(VALID_EXTRA_DATA);
553 }
554
555 /** Accessor function for store conditional return value.*/
556 uint64_t
557 getExtraData() const
558 {
559 assert(privateFlags.isSet(VALID_EXTRA_DATA));
560 return _extraData;
561 }
562
563 /** Accessor function for store conditional return value.*/
564 void
565 setExtraData(uint64_t extraData)
566 {
567 _extraData = extraData;
568 privateFlags.set(VALID_EXTRA_DATA);
569 }
570
571 bool
572 hasContextId() const
573 {
574 return privateFlags.isSet(VALID_CONTEXT_ID);
575 }
576
577 /** Accessor function for context ID.*/
578 int
579 contextId() const
580 {
581 assert(privateFlags.isSet(VALID_CONTEXT_ID));
582 return _contextId;
583 }
584
585 /** Accessor function for thread ID. */
586 int
587 threadId() const
588 {
589 assert(privateFlags.isSet(VALID_THREAD_ID));
590 return _threadId;
591 }
592
593 void
594 setPC(Addr pc)
595 {
596 privateFlags.set(VALID_PC);
597 _pc = pc;
598 }
599
600 bool
601 hasPC() const
602 {
603 return privateFlags.isSet(VALID_PC);
604 }
605
606 /** Accessor function for pc.*/
607 Addr
608 getPC() const
609 {
610 assert(privateFlags.isSet(VALID_PC));
611 return _pc;
612 }
613
614 /**
615 * Increment/Get the depth at which this request is responded to.
616 * This currently happens when the request misses in any cache level.
617 */
618 void incAccessDepth() { depth++; }
619 int getAccessDepth() const { return depth; }
620
621 /**
622 * Set/Get the time taken for this request to be successfully translated.
623 */
624 void setTranslateLatency() { translateDelta = curTick() - _time; }
625 Tick getTranslateLatency() const { return translateDelta; }
626
627 /**
628 * Set/Get the time taken to complete this request's access, not including
629 * the time to successfully translate the request.
630 */
631 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
632 Tick getAccessLatency() const { return accessDelta; }
633
634 /** Accessor functions for flags. Note that these are for testing
635 only; setting flags should be done via setFlags(). */
636 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
637 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
638 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
639 bool isLLSC() const { return _flags.isSet(LLSC); }
640 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
641 bool isLocked() const { return _flags.isSet(LOCKED); }
642 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
643 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
644 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
645 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
646 bool isSecure() const { return _flags.isSet(SECURE); }
647 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
648};
649
650#endif // __MEM_REQUEST_HH__
|