1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the

--- 57 unchanged lines hidden (view full) ---

80class Request;
81
82typedef Request* RequestPtr;
83typedef uint16_t MasterID;
84
85class Request
86{
87 public:
88 typedef uint32_t FlagsType;
89 typedef uint8_t ArchFlagsType;
90 typedef ::Flags<FlagsType> Flags;
91
92 enum : FlagsType {
93 /**
94 * Architecture specific flags.
95 *
96 * These bits int the flag field are reserved for
97 * architecture-specific code. For example, SPARC uses them to
98 * represent ASIs.
99 */
100 ARCH_BITS = 0x000000FF,
101 /** The request was an instruction fetch. */
102 INST_FETCH = 0x00000100,
103 /** The virtual address is also the physical address. */
104 PHYSICAL = 0x00000200,
105 /**
106 * The request is to an uncacheable address.
107 *
108 * @note Uncacheable accesses may be reordered by CPU models. The
109 * STRICT_ORDER flag should be set if such reordering is
110 * undesirable.
111 */
112 UNCACHEABLE = 0x00000400,
113 /**
114 * The request is required to be strictly ordered by <i>CPU
115 * models</i> and is non-speculative.
116 *
117 * A strictly ordered request is guaranteed to never be
118 * re-ordered or executed speculatively by a CPU model. The
119 * memory system may still reorder requests in caches unless
120 * the UNCACHEABLE flag is set as well.
121 */
122 STRICT_ORDER = 0x00000800,
123 /** This request is to a memory mapped register. */
124 MMAPPED_IPR = 0x00002000,
125 /** This request is a clear exclusive. */
126 CLEAR_LL = 0x00004000,
127 /** This request is made in privileged mode. */
128 PRIVILEGED = 0x00008000,
129
130 /**
131 * This is a write that is targeted and zeroing an entire
132 * cache block. There is no need for a read/modify/write
133 */
134 CACHE_BLOCK_ZERO = 0x00010000,
135
136 /** The request should not cause a memory access. */
137 NO_ACCESS = 0x00080000,
138 /**
139 * This request will lock or unlock the accessed memory. When
140 * used with a load, the access locks the particular chunk of
141 * memory. When used with a store, it unlocks. The rule is
142 * that locked accesses have to be made up of a locked load,
143 * some operation on the data, and then a locked store.
144 */
145 LOCKED_RMW = 0x00100000,
146 /** The request is a Load locked/store conditional. */
147 LLSC = 0x00200000,
148 /** This request is for a memory swap. */
149 MEM_SWAP = 0x00400000,
150 MEM_SWAP_COND = 0x00800000,
151
152 /** The request is a prefetch. */
153 PREFETCH = 0x01000000,
154 /** The request should be prefetched into the exclusive state. */
155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158
159 /**
160 * The request should be handled by the generic IPR code (only
161 * valid together with MMAPPED_IPR)
162 */
163 GENERIC_IPR = 0x08000000,
164
165 /** The request targets the secure memory space. */
166 SECURE = 0x10000000,
167 /** The request is a page table walk */
168 PT_WALK = 0x20000000,
169
170 /**
171 * These flags are *not* cleared when a Request object is
172 * reused (assigned a new address).
173 */
174 STICKY_FLAGS = INST_FETCH
175 };
176

--- 473 unchanged lines hidden (view full) ---

650 only; setting flags should be done via setFlags(). */
651 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
652 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
653 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
654 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
655 bool isLLSC() const { return _flags.isSet(LLSC); }
656 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
657 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
658 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
659 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
660 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
661 bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
662 bool isSecure() const { return _flags.isSet(SECURE); }
663 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
664};
665
666#endif // __MEM_REQUEST_HH__