noncoherent_cache.hh (13350:247e4108a5e8) noncoherent_cache.hh (13358:5e1605b47a21)
1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 111 unchanged lines hidden (view full) ---

120 * needs_writeble parameter is ignored.
121 */
122 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
123 bool needs_writable,
124 bool is_whole_line_write) const override;
125
126 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
127
1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 111 unchanged lines hidden (view full) ---

120 * needs_writeble parameter is ignored.
121 */
122 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
123 bool needs_writable,
124 bool is_whole_line_write) const override;
125
126 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
127
128 void evictBlock(CacheBlk *blk, PacketList &writebacks) override;
129
130 public:
131 NoncoherentCache(const NoncoherentCacheParams *p);
132};
133
134#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__
128 public:
129 NoncoherentCache(const NoncoherentCacheParams *p);
130};
131
132#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__