1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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66struct NoncoherentCacheParams;
67
68/**
69 * A non-coherent cache
70 */
71class NoncoherentCache : public BaseCache
72{
73 protected:
74 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
75 PacketList &writebacks) override;
76
77 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
78 Tick forward_time,
79 Tick request_time) override;
80
81 void recvTimingReq(PacketPtr pkt) override;
82
83 void doWritebacks(PacketList& writebacks,
84 Tick forward_time) override;
85
86 void doWritebacksAtomic(PacketList& writebacks) override;
87
88 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
89 CacheBlk *blk) override;
90
91 void recvTimingResp(PacketPtr pkt) override;
92
93 void recvTimingSnoopReq(PacketPtr pkt) override {
94 panic("Unexpected timing snoop request %s", pkt->print());
95 }
96
97 void recvTimingSnoopResp(PacketPtr pkt) override {
98 panic("Unexpected timing snoop response %s", pkt->print());
99 }
100
101 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
102 PacketList &writebacks) override;
103
104 Tick recvAtomic(PacketPtr pkt) override;
105
106 Tick recvAtomicSnoop(PacketPtr pkt) override {
107 panic("Unexpected atomic snoop request %s", pkt->print());
108 }
109
110 void functionalAccess(PacketPtr pkt, bool from_cpu_side) override;

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