bridge.hh (9542:683991c46ac8) bridge.hh (9786:03a075377221)
1/*
1/*
2 * Copyright (c) 2011-2012 ARM Limited
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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46 * @file
47 * Declaration of a memory-mapped bus bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#ifndef __MEM_BRIDGE_HH__
52#define __MEM_BRIDGE_HH__
53
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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46 * @file
47 * Declaration of a memory-mapped bus bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#ifndef __MEM_BRIDGE_HH__
52#define __MEM_BRIDGE_HH__
53
54#include <list>
54#include <deque>
55
56#include "base/types.hh"
57#include "mem/mem_object.hh"
58#include "params/Bridge.hh"
59
60/**
61 * A bridge is used to interface two different busses (or in general a
62 * memory-mapped master and slave), with buffering for requests and

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79 * state and original source. It has enough information to also
80 * restore the response once it comes back to the bridge.
81 */
82 class RequestState : public Packet::SenderState
83 {
84
85 public:
86
55
56#include "base/types.hh"
57#include "mem/mem_object.hh"
58#include "params/Bridge.hh"
59
60/**
61 * A bridge is used to interface two different busses (or in general a
62 * memory-mapped master and slave), with buffering for requests and

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79 * state and original source. It has enough information to also
80 * restore the response once it comes back to the bridge.
81 */
82 class RequestState : public Packet::SenderState
83 {
84
85 public:
86
87 PortID origSrc;
87 const PortID origSrc;
88
89 RequestState(PortID orig_src) : origSrc(orig_src)
90 { }
91
92 };
93
94 /**
95 * A deferred packet stores a packet along with its scheduled
96 * transmission time
97 */
98 class DeferredPacket
99 {
100
101 public:
102
88
89 RequestState(PortID orig_src) : origSrc(orig_src)
90 { }
91
92 };
93
94 /**
95 * A deferred packet stores a packet along with its scheduled
96 * transmission time
97 */
98 class DeferredPacket
99 {
100
101 public:
102
103 Tick tick;
104 PacketPtr pkt;
103 const Tick tick;
104 const PacketPtr pkt;
105
106 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
107 { }
108 };
109
110 // Forward declaration to allow the slave port to have a pointer
111 class BridgeMasterPort;
112

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126
127 /**
128 * Master port on the other side of the bridge (connected to
129 * the other bus).
130 */
131 BridgeMasterPort& masterPort;
132
133 /** Minimum request delay though this bridge. */
105
106 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
107 { }
108 };
109
110 // Forward declaration to allow the slave port to have a pointer
111 class BridgeMasterPort;
112

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126
127 /**
128 * Master port on the other side of the bridge (connected to
129 * the other bus).
130 */
131 BridgeMasterPort& masterPort;
132
133 /** Minimum request delay though this bridge. */
134 Cycles delay;
134 const Cycles delay;
135
136 /** Address ranges to pass through the bridge */
135
136 /** Address ranges to pass through the bridge */
137 AddrRangeList ranges;
137 const AddrRangeList ranges;
138
139 /**
140 * Response packet queue. Response packets are held in this
141 * queue for a specified delay to model the processing delay
138
139 /**
140 * Response packet queue. Response packets are held in this
141 * queue for a specified delay to model the processing delay
142 * of the bridge.
142 * of the bridge. We use a deque as we need to iterate over
143 * the items for functional accesses.
143 */
144 */
144 std::list<DeferredPacket> transmitList;
145 std::deque<DeferredPacket> transmitList;
145
146 /** Counter to track the outstanding responses. */
147 unsigned int outstandingResponses;
148
149 /** If we should send a retry when space becomes available. */
150 bool retryReq;
151
152 /** Max queue size for reserved responses. */
153 unsigned int respQueueLimit;
154
155 /**
156 * Is this side blocked from accepting new response packets.
157 *
158 * @return true if the reserved space has reached the set limit
159 */
146
147 /** Counter to track the outstanding responses. */
148 unsigned int outstandingResponses;
149
150 /** If we should send a retry when space becomes available. */
151 bool retryReq;
152
153 /** Max queue size for reserved responses. */
154 unsigned int respQueueLimit;
155
156 /**
157 * Is this side blocked from accepting new response packets.
158 *
159 * @return true if the reserved space has reached the set limit
160 */
160 bool respQueueFull();
161 bool respQueueFull() const;
161
162 /**
163 * Handle send event, scheduled when the packet at the head of
164 * the response queue is ready to transmit (for timing
165 * accesses only).
166 */
167 void trySendTiming();
168

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241
242 /**
243 * The slave port on the other side of the bridge (connected
244 * to the other bus).
245 */
246 BridgeSlavePort& slavePort;
247
248 /** Minimum delay though this bridge. */
162
163 /**
164 * Handle send event, scheduled when the packet at the head of
165 * the response queue is ready to transmit (for timing
166 * accesses only).
167 */
168 void trySendTiming();
169

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242
243 /**
244 * The slave port on the other side of the bridge (connected
245 * to the other bus).
246 */
247 BridgeSlavePort& slavePort;
248
249 /** Minimum delay though this bridge. */
249 Cycles delay;
250 const Cycles delay;
250
251 /**
252 * Request packet queue. Request packets are held in this
253 * queue for a specified delay to model the processing delay
251
252 /**
253 * Request packet queue. Request packets are held in this
254 * queue for a specified delay to model the processing delay
254 * of the bridge.
255 * of the bridge. We use a deque as we need to iterate over
256 * the items for functional accesses.
255 */
257 */
256 std::list<DeferredPacket> transmitList;
258 std::deque<DeferredPacket> transmitList;
257
258 /** Max queue size for request packets */
259
260 /** Max queue size for request packets */
259 unsigned int reqQueueLimit;
261 const unsigned int reqQueueLimit;
260
261 /**
262 * Handle send event, scheduled when the packet at the head of
263 * the outbound queue is ready to transmit (for timing
264 * accesses only).
265 */
266 void trySendTiming();
267

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284 BridgeSlavePort& _slavePort, Cycles _delay,
285 int _req_limit);
286
287 /**
288 * Is this side blocked from accepting new request packets.
289 *
290 * @return true if the occupied space has reached the set limit
291 */
262
263 /**
264 * Handle send event, scheduled when the packet at the head of
265 * the outbound queue is ready to transmit (for timing
266 * accesses only).
267 */
268 void trySendTiming();
269

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286 BridgeSlavePort& _slavePort, Cycles _delay,
287 int _req_limit);
288
289 /**
290 * Is this side blocked from accepting new request packets.
291 *
292 * @return true if the occupied space has reached the set limit
293 */
292 bool reqQueueFull();
294 bool reqQueueFull() const;
293
294 /**
295 * Queue a request packet to be sent out later and also schedule
296 * a send if necessary.
297 *
298 * @param pkt a request to send out after a delay
299 * @param when tick when response packet should be sent
300 */

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296 /**
297 * Queue a request packet to be sent out later and also schedule
298 * a send if necessary.
299 *
300 * @param pkt a request to send out after a delay
301 * @param when tick when response packet should be sent
302 */

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