| bridge.hh (9164:d112473185ea) | bridge.hh (9180:ee8d7a51651d) |
|---|---|
| 1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 126 unchanged lines hidden (view full) --- 135 136 /** 137 * Master port on the other side of the bridge (connected to 138 * the other bus). 139 */ 140 BridgeMasterPort& masterPort; 141 142 /** Minimum request delay though this bridge. */ | 1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 126 unchanged lines hidden (view full) --- 135 136 /** 137 * Master port on the other side of the bridge (connected to 138 * the other bus). 139 */ 140 BridgeMasterPort& masterPort; 141 142 /** Minimum request delay though this bridge. */ |
| 143 Tick delay; | 143 Cycles delay; |
| 144 145 /** Address ranges to pass through the bridge */ 146 AddrRangeList ranges; 147 148 /** 149 * Response packet queue. Response packets are held in this 150 * queue for a specified delay to model the processing delay 151 * of the bridge. --- 30 unchanged lines hidden (view full) --- 182 public: 183 184 /** 185 * Constructor for the BridgeSlavePort. 186 * 187 * @param _name the port name including the owner 188 * @param _bridge the structural owner 189 * @param _masterPort the master port on the other side of the bridge | 144 145 /** Address ranges to pass through the bridge */ 146 AddrRangeList ranges; 147 148 /** 149 * Response packet queue. Response packets are held in this 150 * queue for a specified delay to model the processing delay 151 * of the bridge. --- 30 unchanged lines hidden (view full) --- 182 public: 183 184 /** 185 * Constructor for the BridgeSlavePort. 186 * 187 * @param _name the port name including the owner 188 * @param _bridge the structural owner 189 * @param _masterPort the master port on the other side of the bridge |
| 190 * @param _delay the delay from seeing a response to sending it | 190 * @param _delay the delay in cycles from receiving to sending |
| 191 * @param _resp_limit the size of the response queue 192 * @param _ranges a number of address ranges to forward 193 */ 194 BridgeSlavePort(const std::string& _name, Bridge& _bridge, | 191 * @param _resp_limit the size of the response queue 192 * @param _ranges a number of address ranges to forward 193 */ 194 BridgeSlavePort(const std::string& _name, Bridge& _bridge, |
| 195 BridgeMasterPort& _masterPort, int _delay, | 195 BridgeMasterPort& _masterPort, Cycles _delay, |
| 196 int _resp_limit, std::vector<Range<Addr> > _ranges); 197 198 /** 199 * Queue a response packet to be sent out later and also schedule 200 * a send if necessary. 201 * 202 * @param pkt a response to send out after a delay 203 * @param when tick when response packet should be sent --- 46 unchanged lines hidden (view full) --- 250 251 /** 252 * The slave port on the other side of the bridge (connected 253 * to the other bus). 254 */ 255 BridgeSlavePort& slavePort; 256 257 /** Minimum delay though this bridge. */ | 196 int _resp_limit, std::vector<Range<Addr> > _ranges); 197 198 /** 199 * Queue a response packet to be sent out later and also schedule 200 * a send if necessary. 201 * 202 * @param pkt a response to send out after a delay 203 * @param when tick when response packet should be sent --- 46 unchanged lines hidden (view full) --- 250 251 /** 252 * The slave port on the other side of the bridge (connected 253 * to the other bus). 254 */ 255 BridgeSlavePort& slavePort; 256 257 /** Minimum delay though this bridge. */ |
| 258 Tick delay; | 258 Cycles delay; |
| 259 260 /** 261 * Request packet queue. Request packets are held in this 262 * queue for a specified delay to model the processing delay 263 * of the bridge. 264 */ 265 std::list<DeferredPacket> transmitList; 266 --- 14 unchanged lines hidden (view full) --- 281 public: 282 283 /** 284 * Constructor for the BridgeMasterPort. 285 * 286 * @param _name the port name including the owner 287 * @param _bridge the structural owner 288 * @param _slavePort the slave port on the other side of the bridge | 259 260 /** 261 * Request packet queue. Request packets are held in this 262 * queue for a specified delay to model the processing delay 263 * of the bridge. 264 */ 265 std::list<DeferredPacket> transmitList; 266 --- 14 unchanged lines hidden (view full) --- 281 public: 282 283 /** 284 * Constructor for the BridgeMasterPort. 285 * 286 * @param _name the port name including the owner 287 * @param _bridge the structural owner 288 * @param _slavePort the slave port on the other side of the bridge |
| 289 * @param _delay the delay from seeing a request to sending it | 289 * @param _delay the delay in cycles from receiving to sending |
| 290 * @param _req_limit the size of the request queue 291 */ 292 BridgeMasterPort(const std::string& _name, Bridge& _bridge, | 290 * @param _req_limit the size of the request queue 291 */ 292 BridgeMasterPort(const std::string& _name, Bridge& _bridge, |
| 293 BridgeSlavePort& _slavePort, int _delay, | 293 BridgeSlavePort& _slavePort, Cycles _delay, |
| 294 int _req_limit); 295 296 /** 297 * Is this side blocked from accepting new request packets. 298 * 299 * @return true if the occupied space has reached the set limit 300 */ 301 bool reqQueueFull(); --- 51 unchanged lines hidden --- | 294 int _req_limit); 295 296 /** 297 * Is this side blocked from accepting new request packets. 298 * 299 * @return true if the occupied space has reached the set limit 300 */ 301 bool reqQueueFull(); --- 51 unchanged lines hidden --- |