1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Steve Reinhardt
42 * Andreas Hansson
43 */
44
45/**
46 * @file
47 * Declaration of a memory-mapped bus bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#ifndef __MEM_BRIDGE_HH__
52#define __MEM_BRIDGE_HH__
53
54#include <list>
55#include <queue>
56#include <string>
57
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58#include "base/fast_alloc.hh"
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58#include "base/types.hh"
59#include "mem/mem_object.hh"
60#include "mem/packet.hh"
61#include "mem/port.hh"
62#include "params/Bridge.hh"
63#include "sim/eventq.hh"
64
65/**
66 * A bridge is used to interface two different busses (or in general a
67 * memory-mapped master and slave), with buffering for requests and
68 * responses. The bridge has a fixed delay for packets passing through
69 * it and responds to a fixed set of address ranges.
70 *
71 * The bridge comprises a slave port and a master port, that buffer
72 * outgoing responses and requests respectively. Buffer space is
73 * reserved when a request arrives, also reserving response space
74 * before forwarding the request. An incoming request is always
75 * accepted (recvTiming returns true), but is potentially NACKed if
76 * there is no request space or response space.
77 */
78class Bridge : public MemObject
79{
80 protected:
81
82 /**
83 * A bridge request state stores packets along with their sender
84 * state and original source. It has enough information to also
85 * restore the response once it comes back to the bridge.
86 */
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88 class RequestState : public Packet::SenderState, public FastAlloc
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| 87 class RequestState : public Packet::SenderState |
88 {
89
90 public:
91
92 Packet::SenderState *origSenderState;
93 PortID origSrc;
94
95 RequestState(PacketPtr _pkt)
96 : origSenderState(_pkt->senderState),
97 origSrc(_pkt->getSrc())
98 { }
99
100 void fixResponse(PacketPtr pkt)
101 {
102 assert(pkt->senderState == this);
103 pkt->setDest(origSrc);
104 pkt->senderState = origSenderState;
105 }
106 };
107
108 /**
109 * A deferred request stores a packet along with its scheduled
110 * transmission time, and whether we can expect to see a response
111 * or not.
112 */
113 class DeferredRequest
114 {
115
116 public:
117
118 Tick ready;
119 PacketPtr pkt;
120 bool expectResponse;
121
122 DeferredRequest(PacketPtr _pkt, Tick t)
123 : ready(t), pkt(_pkt), expectResponse(_pkt->needsResponse())
124 { }
125 };
126
127 /**
128 * A deferred response stores a packet along with its scheduled
129 * transmission time. It also contains information of whether the
130 * bridge NACKed the packet to be able to correctly maintain
131 * counters of outstanding responses.
132 */
133 class DeferredResponse {
134
135 public:
136
137 Tick ready;
138 PacketPtr pkt;
139 bool nackedHere;
140
141 DeferredResponse(PacketPtr _pkt, Tick t, bool nack = false)
142 : ready(t), pkt(_pkt), nackedHere(nack)
143 { }
144 };
145
146 // Forward declaration to allow the slave port to have a pointer
147 class BridgeMasterPort;
148
149 /**
150 * The port on the side that receives requests and sends
151 * responses. The slave port has a set of address ranges that it
152 * is responsible for. The slave port also has a buffer for the
153 * responses not yet sent.
154 */
155 class BridgeSlavePort : public SlavePort
156 {
157
158 private:
159
160 /** A pointer to the bridge to which this port belongs. */
161 Bridge *bridge;
162
163 /**
164 * Master port on the other side of the bridge
165 * (connected to the other bus).
166 */
167 BridgeMasterPort& masterPort;
168
169 /** Minimum request delay though this bridge. */
170 Tick delay;
171
172 /** Min delay to respond with a nack. */
173 Tick nackDelay;
174
175 /** Address ranges to pass through the bridge */
176 AddrRangeList ranges;
177
178 /**
179 * Response packet queue. Response packets are held in this
180 * queue for a specified delay to model the processing delay
181 * of the bridge.
182 */
183 std::list<DeferredResponse> responseQueue;
184
185 /** Counter to track the outstanding responses. */
186 unsigned int outstandingResponses;
187
188 /** If we're waiting for a retry to happen. */
189 bool inRetry;
190
191 /** Max queue size for reserved responses. */
192 unsigned int respQueueLimit;
193
194 /**
195 * Is this side blocked from accepting new response packets.
196 *
197 * @return true if the reserved space has reached the set limit
198 */
199 bool respQueueFull();
200
201 /**
202 * Turn the request packet into a NACK response and put it in
203 * the response queue and schedule its transmission.
204 *
205 * @param pkt the request packet to NACK
206 */
207 void nackRequest(PacketPtr pkt);
208
209 /**
210 * Handle send event, scheduled when the packet at the head of
211 * the response queue is ready to transmit (for timing
212 * accesses only).
213 */
214 void trySend();
215
216 /**
217 * Private class for scheduling sending of responses from the
218 * response queue.
219 */
220 class SendEvent : public Event
221 {
222 BridgeSlavePort& port;
223
224 public:
225 SendEvent(BridgeSlavePort& p) : port(p) {}
226 virtual void process() { port.trySend(); }
227 virtual const char *description() const { return "bridge send"; }
228 };
229
230 /** Send event for the response queue. */
231 SendEvent sendEvent;
232
233 public:
234
235 /**
236 * Constructor for the BridgeSlavePort.
237 *
238 * @param _name the port name including the owner
239 * @param _bridge the structural owner
240 * @param _masterPort the master port on the other side of the bridge
241 * @param _delay the delay from seeing a response to sending it
242 * @param _nack_delay the delay from a NACK to sending the response
243 * @param _resp_limit the size of the response queue
244 * @param _ranges a number of address ranges to forward
245 */
246 BridgeSlavePort(const std::string &_name, Bridge *_bridge,
247 BridgeMasterPort& _masterPort, int _delay,
248 int _nack_delay, int _resp_limit,
249 std::vector<Range<Addr> > _ranges);
250
251 /**
252 * Queue a response packet to be sent out later and also schedule
253 * a send if necessary.
254 *
255 * @param pkt a response to send out after a delay
256 */
257 void queueForSendTiming(PacketPtr pkt);
258
259 protected:
260
261 /** When receiving a timing request from the peer port,
262 pass it to the bridge. */
263 virtual bool recvTimingReq(PacketPtr pkt);
264
265 /** When receiving a retry request from the peer port,
266 pass it to the bridge. */
267 virtual void recvRetry();
268
269 /** When receiving a Atomic requestfrom the peer port,
270 pass it to the bridge. */
271 virtual Tick recvAtomic(PacketPtr pkt);
272
273 /** When receiving a Functional request from the peer port,
274 pass it to the bridge. */
275 virtual void recvFunctional(PacketPtr pkt);
276
277 /** When receiving a address range request the peer port,
278 pass it to the bridge. */
279 virtual AddrRangeList getAddrRanges();
280 };
281
282
283 /**
284 * Port on the side that forwards requests and receives
285 * responses. The master port has a buffer for the requests not
286 * yet sent.
287 */
288 class BridgeMasterPort : public MasterPort
289 {
290
291 private:
292
293 /** A pointer to the bridge to which this port belongs. */
294 Bridge* bridge;
295
296 /**
297 * Pointer to the slave port on the other side of the bridge
298 * (connected to the other bus).
299 */
300 BridgeSlavePort& slavePort;
301
302 /** Minimum delay though this bridge. */
303 Tick delay;
304
305 /**
306 * Request packet queue. Request packets are held in this
307 * queue for a specified delay to model the processing delay
308 * of the bridge.
309 */
310 std::list<DeferredRequest> requestQueue;
311
312 /** If we're waiting for a retry to happen. */
313 bool inRetry;
314
315 /** Max queue size for request packets */
316 unsigned int reqQueueLimit;
317
318 /**
319 * Handle send event, scheduled when the packet at the head of
320 * the outbound queue is ready to transmit (for timing
321 * accesses only).
322 */
323 void trySend();
324
325 /**
326 * Private class for scheduling sending of requests from the
327 * request queue.
328 */
329 class SendEvent : public Event
330 {
331 BridgeMasterPort& port;
332
333 public:
334 SendEvent(BridgeMasterPort& p) : port(p) {}
335 virtual void process() { port.trySend(); }
336 virtual const char *description() const { return "bridge send"; }
337 };
338
339 /** Send event for the request queue. */
340 SendEvent sendEvent;
341
342 public:
343
344 /**
345 * Constructor for the BridgeMasterPort.
346 *
347 * @param _name the port name including the owner
348 * @param _bridge the structural owner
349 * @param _slavePort the slave port on the other side of the bridge
350 * @param _delay the delay from seeing a request to sending it
351 * @param _req_limit the size of the request queue
352 */
353 BridgeMasterPort(const std::string &_name, Bridge *_bridge,
354 BridgeSlavePort& _slavePort, int _delay,
355 int _req_limit);
356
357 /**
358 * Is this side blocked from accepting new request packets.
359 *
360 * @return true if the occupied space has reached the set limit
361 */
362 bool reqQueueFull();
363
364 /**
365 * Queue a request packet to be sent out later and also schedule
366 * a send if necessary.
367 *
368 * @param pkt a request to send out after a delay
369 */
370 void queueForSendTiming(PacketPtr pkt);
371
372 /**
373 * Check a functional request against the packets in our
374 * request queue.
375 *
376 * @param pkt packet to check against
377 *
378 * @return true if we find a match
379 */
380 bool checkFunctional(PacketPtr pkt);
381
382 protected:
383
384 /** When receiving a timing request from the peer port,
385 pass it to the bridge. */
386 virtual bool recvTimingResp(PacketPtr pkt);
387
388 /** When receiving a retry request from the peer port,
389 pass it to the bridge. */
390 virtual void recvRetry();
391 };
392
393 /** Slave port of the bridge. */
394 BridgeSlavePort slavePort;
395
396 /** Master port of the bridge. */
397 BridgeMasterPort masterPort;
398
399 /** If this bridge should acknowledge writes. */
400 bool ackWrites;
401
402 public:
403 typedef BridgeParams Params;
404
405 protected:
406 Params *_params;
407
408 public:
409 const Params *params() const { return _params; }
410
411 virtual MasterPort& getMasterPort(const std::string& if_name,
412 int idx = -1);
413 virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
414
415 virtual void init();
416
417 Bridge(Params *p);
418};
419
420#endif //__MEM_BUS_HH__
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