SConscript (8981:6f4ec692716f) SConscript (9036:6385cf85bf12)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 23 unchanged lines hidden (view full) ---

32
33SimObject('Bridge.py')
34SimObject('Bus.py')
35SimObject('CommMonitor.py')
36SimObject('MemObject.py')
37
38Source('bridge.cc')
39Source('bus.cc')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 23 unchanged lines hidden (view full) ---

32
33SimObject('Bridge.py')
34SimObject('Bus.py')
35SimObject('CommMonitor.py')
36SimObject('MemObject.py')
37
38Source('bridge.cc')
39Source('bus.cc')
40Source('coherent_bus.cc')
40Source('comm_monitor.cc')
41Source('mem_object.cc')
42Source('mport.cc')
41Source('comm_monitor.cc')
42Source('mem_object.cc')
43Source('mport.cc')
44Source('noncoherent_bus.cc')
43Source('packet.cc')
44Source('port.cc')
45Source('packet_queue.cc')
46Source('tport.cc')
47Source('port_proxy.cc')
48Source('fs_translating_port_proxy.cc')
49Source('se_translating_port_proxy.cc')
50
51if env['TARGET_ISA'] != 'no':
52 SimObject('AbstractMemory.py')
53 SimObject('SimpleMemory.py')
54 Source('abstract_mem.cc')
55 Source('simple_mem.cc')
56 Source('page_table.cc')
57 Source('physical.cc')
58
45Source('packet.cc')
46Source('port.cc')
47Source('packet_queue.cc')
48Source('tport.cc')
49Source('port_proxy.cc')
50Source('fs_translating_port_proxy.cc')
51Source('se_translating_port_proxy.cc')
52
53if env['TARGET_ISA'] != 'no':
54 SimObject('AbstractMemory.py')
55 SimObject('SimpleMemory.py')
56 Source('abstract_mem.cc')
57 Source('simple_mem.cc')
58 Source('page_table.cc')
59 Source('physical.cc')
60
59DebugFlag('Bus')
61DebugFlag('BaseBus')
60DebugFlag('BusAddrRanges')
62DebugFlag('BusAddrRanges')
63DebugFlag('CoherentBus')
64DebugFlag('NoncoherentBus')
65CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
66 'NoncoherentBus'])
67
61DebugFlag('BusBridge')
62DebugFlag('CommMonitor')
63DebugFlag('LLSC')
64DebugFlag('MMU')
65DebugFlag('MemoryAccess')
66DebugFlag('PacketQueue')
67
68DebugFlag('ProtocolTrace')

--- 16 unchanged lines hidden --- 		68DebugFlag('BusBridge')
69DebugFlag('CommMonitor')
70DebugFlag('LLSC')
71DebugFlag('MMU')
72DebugFlag('MemoryAccess')
73DebugFlag('PacketQueue')
74
75DebugFlag('ProtocolTrace')

--- 16 unchanged lines hidden ---