SConscript (11184:07b0dacf27d6) SConscript (11185:0ff78be3bc67)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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38SimObject('Bridge.py')
39SimObject('DRAMCtrl.py')
40SimObject('ExternalMaster.py')
41SimObject('ExternalSlave.py')
42SimObject('MemObject.py')
43SimObject('SimpleMemory.py')
44SimObject('XBar.py')
45SimObject('HMCController.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 29 unchanged lines hidden (view full) ---

38SimObject('Bridge.py')
39SimObject('DRAMCtrl.py')
40SimObject('ExternalMaster.py')
41SimObject('ExternalSlave.py')
42SimObject('MemObject.py')
43SimObject('SimpleMemory.py')
44SimObject('XBar.py')
45SimObject('HMCController.py')
46SimObject('SerialLink.py')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('coherent_xbar.cc')
51Source('drampower.cc')
52Source('dram_ctrl.cc')
53Source('external_master.cc')

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61Source('port_proxy.cc')
62Source('physical.cc')
63Source('simple_mem.cc')
64Source('snoop_filter.cc')
65Source('stack_dist_calc.cc')
66Source('tport.cc')
67Source('xbar.cc')
68Source('hmc_controller.cc')
47
48Source('abstract_mem.cc')
49Source('addr_mapper.cc')
50Source('bridge.cc')
51Source('coherent_xbar.cc')
52Source('drampower.cc')
53Source('dram_ctrl.cc')
54Source('external_master.cc')

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62Source('port_proxy.cc')
63Source('physical.cc')
64Source('simple_mem.cc')
65Source('snoop_filter.cc')
66Source('stack_dist_calc.cc')
67Source('tport.cc')
68Source('xbar.cc')
69Source('hmc_controller.cc')
70Source('serial_link.cc')
69
70if env['TARGET_ISA'] != 'null':
71 Source('fs_translating_port_proxy.cc')
72 Source('se_translating_port_proxy.cc')
73 Source('page_table.cc')
74if env['TARGET_ISA'] == 'x86':
75 Source('multi_level_page_table.cc')
76

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99DebugFlag('ExternalPort')
100DebugFlag('LLSC')
101DebugFlag('MMU')
102DebugFlag('MemoryAccess')
103DebugFlag('PacketQueue')
104DebugFlag('StackDist')
105DebugFlag("DRAMSim2")
106DebugFlag('HMCController')
71
72if env['TARGET_ISA'] != 'null':
73 Source('fs_translating_port_proxy.cc')
74 Source('se_translating_port_proxy.cc')
75 Source('page_table.cc')
76if env['TARGET_ISA'] == 'x86':
77 Source('multi_level_page_table.cc')
78

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101DebugFlag('ExternalPort')
102DebugFlag('LLSC')
103DebugFlag('MMU')
104DebugFlag('MemoryAccess')
105DebugFlag('PacketQueue')
106DebugFlag('StackDist')
107DebugFlag("DRAMSim2")
108DebugFlag('HMCController')
109DebugFlag('SerialLink')
107
108DebugFlag("MemChecker")
109DebugFlag("MemCheckerMonitor")
110
111DebugFlag("MemChecker")
112DebugFlag("MemCheckerMonitor")