SConscript (10996:d48fda705f4d) SConscript (11184:07b0dacf27d6)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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37SimObject('AddrMapper.py')
38SimObject('Bridge.py')
39SimObject('DRAMCtrl.py')
40SimObject('ExternalMaster.py')
41SimObject('ExternalSlave.py')
42SimObject('MemObject.py')
43SimObject('SimpleMemory.py')
44SimObject('XBar.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 28 unchanged lines hidden (view full) ---

37SimObject('AddrMapper.py')
38SimObject('Bridge.py')
39SimObject('DRAMCtrl.py')
40SimObject('ExternalMaster.py')
41SimObject('ExternalSlave.py')
42SimObject('MemObject.py')
43SimObject('SimpleMemory.py')
44SimObject('XBar.py')
45SimObject('HMCController.py')
45
46Source('abstract_mem.cc')
47Source('addr_mapper.cc')
48Source('bridge.cc')
49Source('coherent_xbar.cc')
50Source('drampower.cc')
51Source('dram_ctrl.cc')
52Source('external_master.cc')

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59Source('packet_queue.cc')
60Source('port_proxy.cc')
61Source('physical.cc')
62Source('simple_mem.cc')
63Source('snoop_filter.cc')
64Source('stack_dist_calc.cc')
65Source('tport.cc')
66Source('xbar.cc')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('coherent_xbar.cc')
51Source('drampower.cc')
52Source('dram_ctrl.cc')
53Source('external_master.cc')

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60Source('packet_queue.cc')
61Source('port_proxy.cc')
62Source('physical.cc')
63Source('simple_mem.cc')
64Source('snoop_filter.cc')
65Source('stack_dist_calc.cc')
66Source('tport.cc')
67Source('xbar.cc')
68Source('hmc_controller.cc')
67
68if env['TARGET_ISA'] != 'null':
69 Source('fs_translating_port_proxy.cc')
70 Source('se_translating_port_proxy.cc')
71 Source('page_table.cc')
72if env['TARGET_ISA'] == 'x86':
73 Source('multi_level_page_table.cc')
74

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96DebugFlag('DRAMState')
97DebugFlag('ExternalPort')
98DebugFlag('LLSC')
99DebugFlag('MMU')
100DebugFlag('MemoryAccess')
101DebugFlag('PacketQueue')
102DebugFlag('StackDist')
103DebugFlag("DRAMSim2")
69
70if env['TARGET_ISA'] != 'null':
71 Source('fs_translating_port_proxy.cc')
72 Source('se_translating_port_proxy.cc')
73 Source('page_table.cc')
74if env['TARGET_ISA'] == 'x86':
75 Source('multi_level_page_table.cc')
76

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98DebugFlag('DRAMState')
99DebugFlag('ExternalPort')
100DebugFlag('LLSC')
101DebugFlag('MMU')
102DebugFlag('MemoryAccess')
103DebugFlag('PacketQueue')
104DebugFlag('StackDist')
105DebugFlag("DRAMSim2")
106DebugFlag('HMCController')
104
105DebugFlag("MemChecker")
106DebugFlag("MemCheckerMonitor")
107
108DebugFlag("MemChecker")
109DebugFlag("MemCheckerMonitor")