SConscript (10612:6332c9d471a8) SConscript (10614:da37aec3ed1a)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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39SimObject('AbstractMemory.py')
40SimObject('AddrMapper.py')
41SimObject('Bridge.py')
42SimObject('DRAMCtrl.py')
43SimObject('ExternalMaster.py')
44SimObject('ExternalSlave.py')
45SimObject('MemObject.py')
46SimObject('SimpleMemory.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 30 unchanged lines hidden (view full) ---

39SimObject('AbstractMemory.py')
40SimObject('AddrMapper.py')
41SimObject('Bridge.py')
42SimObject('DRAMCtrl.py')
43SimObject('ExternalMaster.py')
44SimObject('ExternalSlave.py')
45SimObject('MemObject.py')
46SimObject('SimpleMemory.py')
47SimObject('StackDistCalc.py')
47SimObject('XBar.py')
48
49Source('abstract_mem.cc')
50Source('addr_mapper.cc')
51Source('bridge.cc')
52Source('coherent_xbar.cc')
53Source('drampower.cc')
54Source('dram_ctrl.cc')

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59Source('noncoherent_xbar.cc')
60Source('packet.cc')
61Source('port.cc')
62Source('packet_queue.cc')
63Source('port_proxy.cc')
64Source('physical.cc')
65Source('simple_mem.cc')
66Source('snoop_filter.cc')
48SimObject('XBar.py')
49
50Source('abstract_mem.cc')
51Source('addr_mapper.cc')
52Source('bridge.cc')
53Source('coherent_xbar.cc')
54Source('drampower.cc')
55Source('dram_ctrl.cc')

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60Source('noncoherent_xbar.cc')
61Source('packet.cc')
62Source('port.cc')
63Source('packet_queue.cc')
64Source('port_proxy.cc')
65Source('physical.cc')
66Source('simple_mem.cc')
67Source('snoop_filter.cc')
68Source('stack_dist_calc.cc')
67Source('tport.cc')
68Source('xbar.cc')
69
70if env['TARGET_ISA'] != 'null':
71 Source('fs_translating_port_proxy.cc')
72 Source('se_translating_port_proxy.cc')
73 Source('page_table.cc')
74if env['TARGET_ISA'] == 'x86':

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96DebugFlag('DRAM')
97DebugFlag('DRAMPower')
98DebugFlag('DRAMState')
99DebugFlag('ExternalPort')
100DebugFlag('LLSC')
101DebugFlag('MMU')
102DebugFlag('MemoryAccess')
103DebugFlag('PacketQueue')
69Source('tport.cc')
70Source('xbar.cc')
71
72if env['TARGET_ISA'] != 'null':
73 Source('fs_translating_port_proxy.cc')
74 Source('se_translating_port_proxy.cc')
75 Source('page_table.cc')
76if env['TARGET_ISA'] == 'x86':

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98DebugFlag('DRAM')
99DebugFlag('DRAMPower')
100DebugFlag('DRAMState')
101DebugFlag('ExternalPort')
102DebugFlag('LLSC')
103DebugFlag('MMU')
104DebugFlag('MemoryAccess')
105DebugFlag('PacketQueue')
104
106DebugFlag('StackDist')
105DebugFlag("DRAMSim2")
106
107DebugFlag("MemChecker")
108DebugFlag("MemCheckerMonitor")
107DebugFlag("DRAMSim2")
108
109DebugFlag("MemChecker")
110DebugFlag("MemCheckerMonitor")