SConscript (10431:d9415c7f61a9) SConscript (10478:7135f938ff28)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 26 unchanged lines hidden (view full) ---

35if env['HAVE_PROTOBUF']:
36 SimObject('CommMonitor.py')
37 Source('comm_monitor.cc')
38
39SimObject('AbstractMemory.py')
40SimObject('AddrMapper.py')
41SimObject('Bridge.py')
42SimObject('DRAMCtrl.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 26 unchanged lines hidden (view full) ---

35if env['HAVE_PROTOBUF']:
36 SimObject('CommMonitor.py')
37 Source('comm_monitor.cc')
38
39SimObject('AbstractMemory.py')
40SimObject('AddrMapper.py')
41SimObject('Bridge.py')
42SimObject('DRAMCtrl.py')
43SimObject('ExternalMaster.py')
44SimObject('ExternalSlave.py')
43SimObject('MemObject.py')
44SimObject('SimpleMemory.py')
45SimObject('XBar.py')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('coherent_xbar.cc')
51Source('drampower.cc')
52Source('dram_ctrl.cc')
45SimObject('MemObject.py')
46SimObject('SimpleMemory.py')
47SimObject('XBar.py')
48
49Source('abstract_mem.cc')
50Source('addr_mapper.cc')
51Source('bridge.cc')
52Source('coherent_xbar.cc')
53Source('drampower.cc')
54Source('dram_ctrl.cc')
55Source('external_master.cc')
56Source('external_slave.cc')
53Source('mem_object.cc')
54Source('mport.cc')
55Source('noncoherent_xbar.cc')
56Source('packet.cc')
57Source('port.cc')
58Source('packet_queue.cc')
59Source('port_proxy.cc')
60Source('physical.cc')

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83CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
84 'SnoopFilter'])
85
86DebugFlag('Bridge')
87DebugFlag('CommMonitor')
88DebugFlag('DRAM')
89DebugFlag('DRAMPower')
90DebugFlag('DRAMState')
57Source('mem_object.cc')
58Source('mport.cc')
59Source('noncoherent_xbar.cc')
60Source('packet.cc')
61Source('port.cc')
62Source('packet_queue.cc')
63Source('port_proxy.cc')
64Source('physical.cc')

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87CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
88 'SnoopFilter'])
89
90DebugFlag('Bridge')
91DebugFlag('CommMonitor')
92DebugFlag('DRAM')
93DebugFlag('DRAMPower')
94DebugFlag('DRAMState')
95DebugFlag('ExternalPort')
91DebugFlag('LLSC')
92DebugFlag('MMU')
93DebugFlag('MemoryAccess')
94DebugFlag('PacketQueue')
95
96DebugFlag("DRAMSim2")
96DebugFlag('LLSC')
97DebugFlag('MMU')
98DebugFlag('MemoryAccess')
99DebugFlag('PacketQueue')
100
101DebugFlag("DRAMSim2")