SConscript (10399:0644819fc32f) | SConscript (10405:7a618c07e663) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 25 unchanged lines hidden (view full) --- 34# tracing relies on it 35if env['HAVE_PROTOBUF']: 36 SimObject('CommMonitor.py') 37 Source('comm_monitor.cc') 38 39SimObject('AbstractMemory.py') 40SimObject('AddrMapper.py') 41SimObject('Bridge.py') | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 25 unchanged lines hidden (view full) --- 34# tracing relies on it 35if env['HAVE_PROTOBUF']: 36 SimObject('CommMonitor.py') 37 Source('comm_monitor.cc') 38 39SimObject('AbstractMemory.py') 40SimObject('AddrMapper.py') 41SimObject('Bridge.py') |
42SimObject('Bus.py') | |
43SimObject('DRAMCtrl.py') 44SimObject('MemObject.py') 45SimObject('SimpleMemory.py') | 42SimObject('DRAMCtrl.py') 43SimObject('MemObject.py') 44SimObject('SimpleMemory.py') |
45SimObject('XBar.py') |
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46 47Source('abstract_mem.cc') 48Source('addr_mapper.cc') 49Source('bridge.cc') | 46 47Source('abstract_mem.cc') 48Source('addr_mapper.cc') 49Source('bridge.cc') |
50Source('bus.cc') 51Source('coherent_bus.cc') | 50Source('coherent_xbar.cc') |
52Source('dram_ctrl.cc') 53Source('mem_object.cc') 54Source('mport.cc') | 51Source('dram_ctrl.cc') 52Source('mem_object.cc') 53Source('mport.cc') |
55Source('noncoherent_bus.cc') | 54Source('noncoherent_xbar.cc') |
56Source('packet.cc') 57Source('port.cc') 58Source('packet_queue.cc') | 55Source('packet.cc') 56Source('port.cc') 57Source('packet_queue.cc') |
59Source('tport.cc') | |
60Source('port_proxy.cc') | 58Source('port_proxy.cc') |
61Source('simple_mem.cc') | |
62Source('physical.cc') | 59Source('physical.cc') |
60Source('simple_mem.cc') |
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63Source('snoop_filter.cc') | 61Source('snoop_filter.cc') |
62Source('tport.cc') 63Source('xbar.cc') |
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64 65if env['TARGET_ISA'] != 'null': 66 Source('fs_translating_port_proxy.cc') 67 Source('se_translating_port_proxy.cc') 68 Source('page_table.cc') 69if env['TARGET_ISA'] == 'x86': 70 Source('multi_level_page_table.cc') 71 72if env['HAVE_DRAMSIM']: 73 SimObject('DRAMSim2.py') 74 Source('dramsim2_wrapper.cc') 75 Source('dramsim2.cc') 76 | 64 65if env['TARGET_ISA'] != 'null': 66 Source('fs_translating_port_proxy.cc') 67 Source('se_translating_port_proxy.cc') 68 Source('page_table.cc') 69if env['TARGET_ISA'] == 'x86': 70 Source('multi_level_page_table.cc') 71 72if env['HAVE_DRAMSIM']: 73 SimObject('DRAMSim2.py') 74 Source('dramsim2_wrapper.cc') 75 Source('dramsim2.cc') 76 |
77DebugFlag('BaseBus') 78DebugFlag('BusAddrRanges') 79DebugFlag('CoherentBus') 80DebugFlag('NoncoherentBus') | 77DebugFlag('AddrRanges') 78DebugFlag('BaseXBar') 79DebugFlag('CoherentXBar') 80DebugFlag('NoncoherentXBar') |
81DebugFlag('SnoopFilter') | 81DebugFlag('SnoopFilter') |
82CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', 83 'NoncoherentBus', 'SnoopFilter']) | 82CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar', 83 'SnoopFilter']) |
84 85DebugFlag('Bridge') 86DebugFlag('CommMonitor') 87DebugFlag('DRAM') 88DebugFlag('DRAMPower') 89DebugFlag('DRAMState') 90DebugFlag('LLSC') 91DebugFlag('MMU') 92DebugFlag('MemoryAccess') 93DebugFlag('PacketQueue') 94 95DebugFlag("DRAMSim2") | 84 85DebugFlag('Bridge') 86DebugFlag('CommMonitor') 87DebugFlag('DRAM') 88DebugFlag('DRAMPower') 89DebugFlag('DRAMState') 90DebugFlag('LLSC') 91DebugFlag('MMU') 92DebugFlag('MemoryAccess') 93DebugFlag('PacketQueue') 94 95DebugFlag("DRAMSim2") |