SConscript (10133:0749c3ec92f4) SConscript (10146:27dfed4c8403)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 26 unchanged lines hidden (view full) ---

35if env['HAVE_PROTOBUF']:
36 SimObject('CommMonitor.py')
37 Source('comm_monitor.cc')
38
39SimObject('AbstractMemory.py')
40SimObject('AddrMapper.py')
41SimObject('Bridge.py')
42SimObject('Bus.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 26 unchanged lines hidden (view full) ---

35if env['HAVE_PROTOBUF']:
36 SimObject('CommMonitor.py')
37 Source('comm_monitor.cc')
38
39SimObject('AbstractMemory.py')
40SimObject('AddrMapper.py')
41SimObject('Bridge.py')
42SimObject('Bus.py')
43SimObject('DRAMCtrl.py')
43SimObject('MemObject.py')
44SimObject('SimpleMemory.py')
44SimObject('MemObject.py')
45SimObject('SimpleMemory.py')
45SimObject('SimpleDRAM.py')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('bus.cc')
51Source('coherent_bus.cc')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('bus.cc')
51Source('coherent_bus.cc')
52Source('dram_ctrl.cc')
52Source('mem_object.cc')
53Source('mport.cc')
54Source('noncoherent_bus.cc')
55Source('packet.cc')
56Source('port.cc')
57Source('packet_queue.cc')
58Source('tport.cc')
59Source('port_proxy.cc')
60Source('simple_mem.cc')
61Source('physical.cc')
53Source('mem_object.cc')
54Source('mport.cc')
55Source('noncoherent_bus.cc')
56Source('packet.cc')
57Source('port.cc')
58Source('packet_queue.cc')
59Source('tport.cc')
60Source('port_proxy.cc')
61Source('simple_mem.cc')
62Source('physical.cc')
62Source('simple_dram.cc')
63
64if env['TARGET_ISA'] != 'null':
65 Source('fs_translating_port_proxy.cc')
66 Source('se_translating_port_proxy.cc')
67 Source('page_table.cc')
68
69if env['HAVE_DRAMSIM']:
70 SimObject('DRAMSim2.py')

--- 19 unchanged lines hidden --- 		63
64if env['TARGET_ISA'] != 'null':
65 Source('fs_translating_port_proxy.cc')
66 Source('se_translating_port_proxy.cc')
67 Source('page_table.cc')
68
69if env['HAVE_DRAMSIM']:
70 SimObject('DRAMSim2.py')

--- 19 unchanged lines hidden ---