1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 30 unchanged lines hidden (view full) --- 39SimObject('DRAMCtrl.py') 40SimObject('ExternalMaster.py') 41SimObject('ExternalSlave.py') 42SimObject('MemObject.py') 43SimObject('SimpleMemory.py') 44SimObject('XBar.py') 45SimObject('HMCController.py') 46SimObject('SerialLink.py') |
47SimObject('MemDelay.py') |
48 49Source('abstract_mem.cc') 50Source('addr_mapper.cc') 51Source('bridge.cc') 52Source('coherent_xbar.cc') 53Source('drampower.cc') 54Source('dram_ctrl.cc') 55Source('external_master.cc') --- 8 unchanged lines hidden (view full) --- 64Source('physical.cc') 65Source('simple_mem.cc') 66Source('snoop_filter.cc') 67Source('stack_dist_calc.cc') 68Source('tport.cc') 69Source('xbar.cc') 70Source('hmc_controller.cc') 71Source('serial_link.cc') |
72Source('mem_delay.cc') |
73 74if env['TARGET_ISA'] != 'null': 75 Source('fs_translating_port_proxy.cc') 76 Source('se_translating_port_proxy.cc') 77 Source('page_table.cc') 78 79if env['HAVE_DRAMSIM']: 80 SimObject('DRAMSim2.py') --- 32 unchanged lines hidden --- |