| 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 30 unchanged lines hidden (view full) --- 39SimObject('AbstractMemory.py') 40SimObject('AddrMapper.py') 41SimObject('Bridge.py') 42SimObject('DRAMCtrl.py') 43SimObject('ExternalMaster.py') 44SimObject('ExternalSlave.py') 45SimObject('MemObject.py') 46SimObject('SimpleMemory.py') |
| 47SimObject('XBar.py') 48 49Source('abstract_mem.cc') 50Source('addr_mapper.cc') 51Source('bridge.cc') 52Source('coherent_xbar.cc') 53Source('drampower.cc') 54Source('dram_ctrl.cc') --- 55 unchanged lines hidden --- |