1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 46 unchanged lines hidden (view full) --- 55Source('noncoherent_bus.cc') 56Source('packet.cc') 57Source('port.cc') 58Source('packet_queue.cc') 59Source('tport.cc') 60Source('port_proxy.cc') 61Source('simple_mem.cc') 62Source('physical.cc') |
63Source('snoop_filter.cc') |
64 65if env['TARGET_ISA'] != 'null': 66 Source('fs_translating_port_proxy.cc') 67 Source('se_translating_port_proxy.cc') 68 Source('page_table.cc') 69if env['TARGET_ISA'] == 'x86': 70 Source('multi_level_page_table.cc') 71 72if env['HAVE_DRAMSIM']: 73 SimObject('DRAMSim2.py') 74 Source('dramsim2_wrapper.cc') 75 Source('dramsim2.cc') 76 77DebugFlag('BaseBus') 78DebugFlag('BusAddrRanges') 79DebugFlag('CoherentBus') 80DebugFlag('NoncoherentBus') |
81DebugFlag('SnoopFilter') |
82CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', |
83 'NoncoherentBus', 'SnoopFilter']) |
84 85DebugFlag('Bridge') 86DebugFlag('CommMonitor') 87DebugFlag('DRAM') 88DebugFlag('DRAMPower') 89DebugFlag('DRAMState') 90DebugFlag('LLSC') 91DebugFlag('MMU') 92DebugFlag('MemoryAccess') 93DebugFlag('PacketQueue') 94 95DebugFlag("DRAMSim2") |