3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('CommMonitor.py')
34Source('comm_monitor.cc')
35
36SimObject('AbstractMemory.py')
37SimObject('AddrMapper.py')
38SimObject('Bridge.py')
39SimObject('DRAMCtrl.py')
40SimObject('ExternalMaster.py')
41SimObject('ExternalSlave.py')
42SimObject('MemObject.py')
43SimObject('SimpleMemory.py')
44SimObject('XBar.py')
45SimObject('HMCController.py')
46SimObject('SerialLink.py')
47SimObject('MemDelay.py')
48
49Source('abstract_mem.cc')
50Source('addr_mapper.cc')
51Source('bridge.cc')
52Source('coherent_xbar.cc')
53Source('drampower.cc')
54Source('dram_ctrl.cc')
55Source('external_master.cc')
56Source('external_slave.cc')
57Source('mem_object.cc')
58Source('mport.cc')
59Source('noncoherent_xbar.cc')
60Source('packet.cc')
61Source('port.cc')
62Source('packet_queue.cc')
63Source('port_proxy.cc')
64Source('physical.cc')
65Source('simple_mem.cc')
66Source('snoop_filter.cc')
67Source('stack_dist_calc.cc')
68Source('tport.cc')
69Source('xbar.cc')
70Source('hmc_controller.cc')
71Source('serial_link.cc')
72Source('mem_delay.cc')
73
74if env['TARGET_ISA'] != 'null':
75 Source('fs_translating_port_proxy.cc')
76 Source('se_translating_port_proxy.cc')
77 Source('page_table.cc')
78
79if env['HAVE_DRAMSIM']:
80 SimObject('DRAMSim2.py')
81 Source('dramsim2_wrapper.cc')
82 Source('dramsim2.cc')
83
84SimObject('MemChecker.py')
85Source('mem_checker.cc')
86Source('mem_checker_monitor.cc')
87
88DebugFlag('AddrRanges')
89DebugFlag('BaseXBar')
90DebugFlag('CoherentXBar')
91DebugFlag('NoncoherentXBar')
92DebugFlag('SnoopFilter')
93CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
94 'SnoopFilter'])
95
96DebugFlag('Bridge')
97DebugFlag('CommMonitor')
98DebugFlag('DRAM')
99DebugFlag('DRAMPower')
100DebugFlag('DRAMState')
101DebugFlag('ExternalPort')
102DebugFlag('LLSC')
103DebugFlag('MMU')
104DebugFlag('MemoryAccess')
105DebugFlag('PacketQueue')
106DebugFlag('StackDist')
107DebugFlag("DRAMSim2")
108DebugFlag('HMCController')
109DebugFlag('SerialLink')
110
111DebugFlag("MemChecker")
112DebugFlag("MemCheckerMonitor")
| 15# Copyright (c) 2006 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Nathan Binkert
42
43Import('*')
44
45SimObject('CommMonitor.py')
46Source('comm_monitor.cc')
47
48SimObject('AbstractMemory.py')
49SimObject('AddrMapper.py')
50SimObject('Bridge.py')
51SimObject('DRAMCtrl.py')
52SimObject('ExternalMaster.py')
53SimObject('ExternalSlave.py')
54SimObject('MemObject.py')
55SimObject('SimpleMemory.py')
56SimObject('XBar.py')
57SimObject('HMCController.py')
58SimObject('SerialLink.py')
59SimObject('MemDelay.py')
60
61Source('abstract_mem.cc')
62Source('addr_mapper.cc')
63Source('bridge.cc')
64Source('coherent_xbar.cc')
65Source('drampower.cc')
66Source('dram_ctrl.cc')
67Source('external_master.cc')
68Source('external_slave.cc')
69Source('mem_object.cc')
70Source('mport.cc')
71Source('noncoherent_xbar.cc')
72Source('packet.cc')
73Source('port.cc')
74Source('packet_queue.cc')
75Source('port_proxy.cc')
76Source('physical.cc')
77Source('simple_mem.cc')
78Source('snoop_filter.cc')
79Source('stack_dist_calc.cc')
80Source('tport.cc')
81Source('xbar.cc')
82Source('hmc_controller.cc')
83Source('serial_link.cc')
84Source('mem_delay.cc')
85
86if env['TARGET_ISA'] != 'null':
87 Source('fs_translating_port_proxy.cc')
88 Source('se_translating_port_proxy.cc')
89 Source('page_table.cc')
90
91if env['HAVE_DRAMSIM']:
92 SimObject('DRAMSim2.py')
93 Source('dramsim2_wrapper.cc')
94 Source('dramsim2.cc')
95
96SimObject('MemChecker.py')
97Source('mem_checker.cc')
98Source('mem_checker_monitor.cc')
99
100DebugFlag('AddrRanges')
101DebugFlag('BaseXBar')
102DebugFlag('CoherentXBar')
103DebugFlag('NoncoherentXBar')
104DebugFlag('SnoopFilter')
105CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
106 'SnoopFilter'])
107
108DebugFlag('Bridge')
109DebugFlag('CommMonitor')
110DebugFlag('DRAM')
111DebugFlag('DRAMPower')
112DebugFlag('DRAMState')
113DebugFlag('ExternalPort')
114DebugFlag('LLSC')
115DebugFlag('MMU')
116DebugFlag('MemoryAccess')
117DebugFlag('PacketQueue')
118DebugFlag('StackDist')
119DebugFlag("DRAMSim2")
120DebugFlag('HMCController')
121DebugFlag('SerialLink')
122
123DebugFlag("MemChecker")
124DebugFlag("MemCheckerMonitor")
|