1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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30
31Import('*')
32
33SimObject('Bridge.py')
34SimObject('Bus.py')
35SimObject('MemObject.py')
36SimObject('PhysicalMemory.py')
37
38if env['RUBY']:
39 SimObject('RubyMemory.py')
40
41Source('bridge.cc')
42Source('bus.cc')
43Source('dram.cc')
44Source('mem_object.cc')
45Source('packet.cc')
46Source('physical.cc')
47Source('port.cc')
48Source('tport.cc')
49Source('mport.cc')
50
51if env['RUBY']:
52 Source('rubymem.cc')
53
54if env['FULL_SYSTEM']:
55 Source('vport.cc')
56else:
57 Source('page_table.cc')
58 Source('translating_port.cc')
59
60TraceFlag('Bus')
61TraceFlag('BusAddrRanges')
62TraceFlag('BusBridge')
63TraceFlag('LLSC')
64TraceFlag('MMU')
65TraceFlag('MemoryAccess')
66TraceFlag('Ruby')