1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('Bridge.py')
34SimObject('Bus.py')
35SimObject('MemObject.py')
36SimObject('PhysicalMemory.py')
37SimObject('RubyMemory.py')
38
39Source('bridge.cc')
40Source('bus.cc')
41Source('dram.cc')
42Source('mem_object.cc')
43Source('packet.cc')
44Source('physical.cc')
45Source('port.cc')
46Source('tport.cc')
47Source('mport.cc')
48Source('rubymem.cc')
49
50if env['FULL_SYSTEM']:
51 Source('vport.cc')
52else:
53 Source('page_table.cc')
54 Source('translating_port.cc')
55
56TraceFlag('Bus')
57TraceFlag('BusAddrRanges')
58TraceFlag('BusBridge')
59TraceFlag('LLSC')
60TraceFlag('MMU')
61TraceFlag('MemoryAccess')