1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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55Source('noncoherent_bus.cc')
56Source('packet.cc')
57Source('port.cc')
58Source('packet_queue.cc')
59Source('tport.cc')
60Source('port_proxy.cc')
61Source('simple_mem.cc')
62Source('physical.cc')
63
64if env['TARGET_ISA'] != 'null':
65 Source('fs_translating_port_proxy.cc')
66 Source('se_translating_port_proxy.cc')
67 Source('page_table.cc')
68if env['TARGET_ISA'] == 'x86':
69 Source('multi_level_page_table.cc')
70
71if env['HAVE_DRAMSIM']:
72 SimObject('DRAMSim2.py')
73 Source('dramsim2_wrapper.cc')
74 Source('dramsim2.cc')
75
76DebugFlag('BaseBus')
77DebugFlag('BusAddrRanges')
78DebugFlag('CoherentBus')
79DebugFlag('NoncoherentBus')
80CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
81 'NoncoherentBus'])
82
83DebugFlag('Bridge')
84DebugFlag('CommMonitor')
85DebugFlag('DRAM')
86DebugFlag('DRAMPower')
87DebugFlag('DRAMState')
88DebugFlag('LLSC')
89DebugFlag('MMU')
90DebugFlag('MemoryAccess')
91DebugFlag('PacketQueue')
92
93DebugFlag("DRAMSim2")