1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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43SimObject('MemObject.py')
44SimObject('SimpleMemory.py')
45SimObject('XBar.py')
46
47Source('abstract_mem.cc')
48Source('addr_mapper.cc')
49Source('bridge.cc')
50Source('coherent_xbar.cc')
51Source('drampower.cc')
52Source('dram_ctrl.cc')
53Source('mem_object.cc')
54Source('mport.cc')
55Source('noncoherent_xbar.cc')
56Source('packet.cc')
57Source('port.cc')
58Source('packet_queue.cc')
59Source('port_proxy.cc')

--- 37 unchanged lines hidden ---