1/* 2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 48 unchanged lines hidden (view full) --- 57 58class GlobalMemPipeline 59{ 60 public: 61 GlobalMemPipeline(const ComputeUnitParams *params); 62 void init(ComputeUnit *cu); 63 void exec(); 64 |
65 std::queue<GPUDynInstPtr> &getGMReqFIFO() { return gmIssuedRequests; } 66 std::queue<GPUDynInstPtr> &getGMStRespFIFO() { return gmReturnedStores; } 67 std::queue<GPUDynInstPtr> &getGMLdRespFIFO() { return gmReturnedLoads; } 68 69 bool 70 isGMLdRespFIFOWrRdy() const 71 { 72 return gmReturnedLoads.size() < gmQueueSize; --- 9 unchanged lines hidden (view full) --- 82 isGMReqFIFOWrRdy(uint32_t pendReqs=0) const 83 { 84 return (gmIssuedRequests.size() + pendReqs) < gmQueueSize; 85 } 86 87 const std::string &name() const { return _name; } 88 void regStats(); 89 |
90 void 91 incLoadVRFBankConflictCycles(int num_cycles) 92 { 93 loadVrfBankConflictCycles += num_cycles; 94 } 95 |
96 private: 97 ComputeUnit *computeUnit; 98 std::string _name; 99 int gmQueueSize; 100 101 // number of cycles of delaying the update of a VGPR that is the 102 // target of a load instruction (or the load component of an atomic) 103 // The delay is due to VRF bank conflicts --- 24 unchanged lines hidden --- |