T1000.py (8742:9df38d259935) T1000.py (8847:ef8630054b5e)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 95 unchanged lines hidden (view full) ---

104 htod = DumbTOD()
105
106 pterm = Terminal()
107 puart0 = Uart8250(pio_addr=0x1f10000000)
108
109 iob = Iob()
110 # Attach I/O devices that are on chip
111 def attachOnChipIO(self, bus):
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 95 unchanged lines hidden (view full) ---

104 htod = DumbTOD()
105
106 pterm = Terminal()
107 puart0 = Uart8250(pio_addr=0x1f10000000)
108
109 iob = Iob()
110 # Attach I/O devices that are on chip
111 def attachOnChipIO(self, bus):
112 self.iob.pio = bus.port
113 self.htod.pio = bus.port
112 self.iob.pio = bus.master
113 self.htod.pio = bus.master
114
115
116 # Attach I/O devices to specified bus object. Can't do this
117 # earlier, since the bus object itself is typically defined at the
118 # System level.
119 def attachIO(self, bus):
120 self.hvuart.terminal = self.hterm
121 self.puart0.terminal = self.pterm
114
115
116 # Attach I/O devices to specified bus object. Can't do this
117 # earlier, since the bus object itself is typically defined at the
118 # System level.
119 def attachIO(self, bus):
120 self.hvuart.terminal = self.hterm
121 self.puart0.terminal = self.pterm
122 self.fake_clk.pio = bus.port
123 self.fake_membnks.pio = bus.port
124 self.fake_l2_1.pio = bus.port
125 self.fake_l2_2.pio = bus.port
126 self.fake_l2_3.pio = bus.port
127 self.fake_l2_4.pio = bus.port
128 self.fake_l2esr_1.pio = bus.port
129 self.fake_l2esr_2.pio = bus.port
130 self.fake_l2esr_3.pio = bus.port
131 self.fake_l2esr_4.pio = bus.port
132 self.fake_ssi.pio = bus.port
133 self.fake_jbi.pio = bus.port
134 self.puart0.pio = bus.port
135 self.hvuart.pio = bus.port
122 self.fake_clk.pio = bus.master
123 self.fake_membnks.pio = bus.master
124 self.fake_l2_1.pio = bus.master
125 self.fake_l2_2.pio = bus.master
126 self.fake_l2_3.pio = bus.master
127 self.fake_l2_4.pio = bus.master
128 self.fake_l2esr_1.pio = bus.master
129 self.fake_l2esr_2.pio = bus.master
130 self.fake_l2esr_3.pio = bus.master
131 self.fake_l2esr_4.pio = bus.master
132 self.fake_ssi.pio = bus.master
133 self.fake_jbi.pio = bus.master
134 self.puart0.pio = bus.master
135 self.hvuart.pio = bus.master