1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
32from Platform import Platform
33from Terminal import Terminal
34from Uart import Uart8250
35
36
37class MmDisk(BasicPioDevice):
38 type = 'MmDisk'
39 image = Param.DiskImage("Disk Image")
40 pio_addr = 0x1F40000000
41
42class DumbTOD(BasicPioDevice):

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93
94 fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
95 ret_data64=0x0000000000000000, update_data=True)
96 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
97
98 fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
99 #warn_access="Accessing SSI -- Unimplemented!")
100
101 hterm = Terminal()
102 hvuart = Uart8250(pio_addr=0xfff0c2c000)
103 htod = DumbTOD()
104
105 pterm = Terminal()
106 puart0 = Uart8250(pio_addr=0x1f10000000)
107
108 iob = Iob()
109 # Attach I/O devices that are on chip
110 def attachOnChipIO(self, bus):
111 self.iob.pio = bus.port
112 self.htod.pio = bus.port
113
114
115 # Attach I/O devices to specified bus object. Can't do this
116 # earlier, since the bus object itself is typically defined at the
117 # System level.
118 def attachIO(self, bus):
119 self.hvuart.terminal = self.hterm
120 self.puart0.terminal = self.pterm
121 self.fake_clk.pio = bus.port
122 self.fake_membnks.pio = bus.port
123 self.fake_l2_1.pio = bus.port
124 self.fake_l2_2.pio = bus.port
125 self.fake_l2_3.pio = bus.port
126 self.fake_l2_4.pio = bus.port
127 self.fake_l2esr_1.pio = bus.port
128 self.fake_l2esr_2.pio = bus.port
129 self.fake_l2esr_3.pio = bus.port
130 self.fake_l2esr_4.pio = bus.port
131 self.fake_ssi.pio = bus.port
132 self.fake_jbi.pio = bus.port
133 self.puart0.pio = bus.port
134 self.hvuart.pio = bus.port