isa_fake.cc (3488:52e909177bfa) isa_fake.cc (3499:597f3f6c9775)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 11 unchanged lines hidden (view full) ---

20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 11 unchanged lines hidden (view full) ---

20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Miguel Serrano
29 * Ali Saidi
28 * Authors: Ali Saidi
30 */
31
32/** @file
33 * Isa Fake Device implementation
34 */
35
29 */
30
31/** @file
32 * Isa Fake Device implementation
33 */
34
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "dev/isa_fake.hh"
42#include "mem/packet.hh"
43#include "mem/packet_access.hh"
44#include "sim/builder.hh"
45#include "sim/system.hh"
46
47using namespace std;
48
49IsaFake::IsaFake(Params *p)
50 : BasicPioDevice(p)
51{
35#include "base/trace.hh"
36#include "dev/isa_fake.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/builder.hh"
40#include "sim/system.hh"
41
42using namespace std;
43
44IsaFake::IsaFake(Params *p)
45 : BasicPioDevice(p)
46{
52 pioSize = p->pio_size;
53}
47 if (!params()->retBadAddr)
48 pioSize = p->pio_size;
54
49
55Tick
56IsaFake::read(PacketPtr pkt)
57{
58 assert(pkt->result == Packet::Unknown);
59 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
60
61 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
62
63 switch (pkt->getSize()) {
64 case sizeof(uint64_t):
65 pkt->set(0xFFFFFFFFFFFFFFFFULL);
66 break;
67 case sizeof(uint32_t):
68 pkt->set((uint32_t)0xFFFFFFFF);
69 break;
70 case sizeof(uint16_t):
71 pkt->set((uint16_t)0xFFFF);
72 break;
73 case sizeof(uint8_t):
74 pkt->set((uint8_t)0xFF);
75 break;
76 default:
77 panic("invalid access size(?) for PCI configspace!\n");
78 }
79 pkt->result = Packet::Success;
80 return pioDelay;
50 memset(&retData, p->retData, sizeof(retData));
81}
82
51}
52
83Tick
84IsaFake::write(PacketPtr pkt)
85{
86 DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
87 pkt->result = Packet::Success;
88 return pioDelay;
89}
90
91BadAddr::BadAddr(Params *p)
92 : BasicPioDevice(p)
93{
94}
95
96void
53void
97BadAddr::init()
54IsaFake::init()
98{
99 // Only init this device if it's connected to anything.
100 if (pioPort)
101 PioDevice::init();
102}
103
55{
56 // Only init this device if it's connected to anything.
57 if (pioPort)
58 PioDevice::init();
59}
60
61
104Tick
62Tick
105BadAddr::read(PacketPtr pkt)
63IsaFake::read(PacketPtr pkt)
106{
107 assert(pkt->result == Packet::Unknown);
64{
65 assert(pkt->result == Packet::Unknown);
108 DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
109 pkt->getAddr(), pkt->getSize());
110 pkt->result = Packet::BadAddress;
66
67 if (params()->retBadAddr) {
68 DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
69 pkt->getAddr(), pkt->getSize());
70 pkt->result = Packet::BadAddress;
71 } else {
72 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
73 DPRINTF(Tsunami, "read va=%#x size=%d\n",
74 pkt->getAddr(), pkt->getSize());
75 switch (pkt->getSize()) {
76 case sizeof(uint64_t):
77 pkt->set(retData);
78 break;
79 case sizeof(uint32_t):
80 pkt->set((uint32_t)retData);
81 break;
82 case sizeof(uint16_t):
83 pkt->set((uint16_t)retData);
84 break;
85 case sizeof(uint8_t):
86 pkt->set((uint8_t)retData);
87 break;
88 default:
89 panic("invalid access size!\n");
90 }
91 pkt->result = Packet::Success;
92 }
111 return pioDelay;
112}
113
114Tick
93 return pioDelay;
94}
95
96Tick
115BadAddr::write(PacketPtr pkt)
97IsaFake::write(PacketPtr pkt)
116{
98{
117 DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
118 pkt->getAddr(), pkt->getSize());
119 pkt->result = Packet::BadAddress;
99 if (params()->retBadAddr) {
100 DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
101 pkt->getAddr(), pkt->getSize());
102 pkt->result = Packet::BadAddress;
103 } else {
104 DPRINTF(Tsunami, "write - va=%#x size=%d \n",
105 pkt->getAddr(), pkt->getSize());
106 pkt->result = Packet::Success;
107 }
120 return pioDelay;
121}
122
123BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
124
125 Param<Addr> pio_addr;
126 Param<Tick> pio_latency;
127 Param<Addr> pio_size;
108 return pioDelay;
109}
110
111BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
112
113 Param<Addr> pio_addr;
114 Param<Tick> pio_latency;
115 Param<Addr> pio_size;
116 Param<bool> ret_bad_addr;
117 Param<uint8_t> ret_data;
128 SimObjectParam<Platform *> platform;
129 SimObjectParam<System *> system;
130
131END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
132
133BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
134
135 INIT_PARAM(pio_addr, "Device Address"),
136 INIT_PARAM(pio_latency, "Programmed IO latency"),
137 INIT_PARAM(pio_size, "Size of address range"),
118 SimObjectParam<Platform *> platform;
119 SimObjectParam<System *> system;
120
121END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
122
123BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
124
125 INIT_PARAM(pio_addr, "Device Address"),
126 INIT_PARAM(pio_latency, "Programmed IO latency"),
127 INIT_PARAM(pio_size, "Size of address range"),
128 INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
129 INIT_PARAM(ret_data, "Data to return if not bad addr"),
138 INIT_PARAM(platform, "platform"),
139 INIT_PARAM(system, "system object")
140
141END_INIT_SIM_OBJECT_PARAMS(IsaFake)
142
143CREATE_SIM_OBJECT(IsaFake)
144{
145 IsaFake::Params *p = new IsaFake::Params;
146 p->name = getInstanceName();
147 p->pio_addr = pio_addr;
148 p->pio_delay = pio_latency;
149 p->pio_size = pio_size;
130 INIT_PARAM(platform, "platform"),
131 INIT_PARAM(system, "system object")
132
133END_INIT_SIM_OBJECT_PARAMS(IsaFake)
134
135CREATE_SIM_OBJECT(IsaFake)
136{
137 IsaFake::Params *p = new IsaFake::Params;
138 p->name = getInstanceName();
139 p->pio_addr = pio_addr;
140 p->pio_delay = pio_latency;
141 p->pio_size = pio_size;
142 p->retBadAddr = ret_bad_addr;
143 p->retData = ret_data;
150 p->platform = platform;
151 p->system = system;
152 return new IsaFake(p);
153}
154
155REGISTER_SIM_OBJECT("IsaFake", IsaFake)
144 p->platform = platform;
145 p->system = system;
146 return new IsaFake(p);
147}
148
149REGISTER_SIM_OBJECT("IsaFake", IsaFake)
156
157BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
158
159 Param<Addr> pio_addr;
160 Param<Tick> pio_latency;
161 SimObjectParam<Platform *> platform;
162 SimObjectParam<System *> system;
163
164END_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
165
166BEGIN_INIT_SIM_OBJECT_PARAMS(BadAddr)
167
168 INIT_PARAM(pio_addr, "Device Address"),
169 INIT_PARAM(pio_latency, "Programmed IO latency"),
170 INIT_PARAM(platform, "platform"),
171 INIT_PARAM(system, "system object")
172
173END_INIT_SIM_OBJECT_PARAMS(BadAddr)
174
175CREATE_SIM_OBJECT(BadAddr)
176{
177 BadAddr::Params *p = new BadAddr::Params;
178 p->name = getInstanceName();
179 p->pio_addr = pio_addr;
180 p->pio_delay = pio_latency;
181 p->platform = platform;
182 p->system = system;
183 return new BadAddr(p);
184}
185
186REGISTER_SIM_OBJECT("BadAddr", BadAddr)