1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 42 unchanged lines hidden (view full) --- 51 retData16 = p->ret_data16; 52 retData32 = p->ret_data32; 53 retData64 = p->ret_data64; 54} 55 56Tick 57IsaFake::read(PacketPtr pkt) 58{ |
59 pkt->allocate(); |
60 pkt->makeAtomicResponse(); |
61 |
62 if (params()->warn_access != "") 63 warn("Device %s accessed by read to address %#x size=%d\n", 64 name(), pkt->getAddr(), pkt->getSize()); 65 if (params()->ret_bad_addr) { 66 DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n", 67 pkt->getAddr(), pkt->getSize()); 68 pkt->setBadAddress(); 69 } else { --- 9 unchanged lines hidden (view full) --- 79 break; 80 case sizeof(uint16_t): 81 pkt->set(retData16); 82 break; 83 case sizeof(uint8_t): 84 pkt->set(retData8); 85 break; 86 default: |
87 if (params()->fake_mem) 88 std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize()); 89 else 90 panic("invalid access size! Device being accessed by cache?\n"); |
91 } 92 } 93 return pioDelay; 94} 95 96Tick 97IsaFake::write(PacketPtr pkt) 98{ --- 57 unchanged lines hidden --- |