kmi.cc (12660:c5caca5f7d68) | kmi.cc (12664:4e4555947641) |
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1/* 2 * Copyright (c) 2010, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 40 unchanged lines hidden (view full) --- 49#include "dev/arm/amba_device.hh" 50#include "dev/ps2/device.hh" 51#include "mem/packet.hh" 52#include "mem/packet_access.hh" 53 54Pl050::Pl050(const Pl050Params *p) 55 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0), 56 rawInterrupts(0), | 1/* 2 * Copyright (c) 2010, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 40 unchanged lines hidden (view full) --- 49#include "dev/arm/amba_device.hh" 50#include "dev/ps2/device.hh" 51#include "mem/packet.hh" 52#include "mem/packet_access.hh" 53 54Pl050::Pl050(const Pl050Params *p) 55 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0), 56 rawInterrupts(0), |
57 intEvent([this]{ generateInterrupt(); }, name()), | |
58 ps2(p->ps2) 59{ | 57 ps2(p->ps2) 58{ |
60 ps2->hostRegDataAvailable([this]() { this->updateIntStatus(); }); | 59 ps2->hostRegDataAvailable([this]() { this->updateRxInt(); }); |
61} 62 63Tick 64Pl050::read(PacketPtr pkt) 65{ 66 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 67 68 Addr daddr = pkt->getAddr() - pioAddr; --- 9 unchanged lines hidden (view full) --- 78 case kmiStat: 79 status.rxfull = ps2->hostDataAvailable() ? 1 : 0; 80 DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status); 81 data = status; 82 break; 83 84 case kmiData: 85 data = ps2->hostDataAvailable() ? ps2->hostRead() : 0; | 60} 61 62Tick 63Pl050::read(PacketPtr pkt) 64{ 65 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 66 67 Addr daddr = pkt->getAddr() - pioAddr; --- 9 unchanged lines hidden (view full) --- 77 case kmiStat: 78 status.rxfull = ps2->hostDataAvailable() ? 1 : 0; 79 DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status); 80 data = status; 81 break; 82 83 case kmiData: 84 data = ps2->hostDataAvailable() ? ps2->hostRead() : 0; |
85 updateRxInt(); |
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86 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data); | 86 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data); |
87 updateIntStatus(); | |
88 break; 89 90 case kmiClkDiv: 91 data = clkdiv; 92 break; 93 94 case kmiISR: 95 data = getInterrupt(); --- 6 unchanged lines hidden (view full) --- 102 data = pkt->get<uint32_t>(); 103 break; 104 } 105 106 warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr); 107 break; 108 } 109 | 87 break; 88 89 case kmiClkDiv: 90 data = clkdiv; 91 break; 92 93 case kmiISR: 94 data = getInterrupt(); --- 6 unchanged lines hidden (view full) --- 101 data = pkt->get<uint32_t>(); 102 break; 103 } 104 105 warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr); 106 break; 107 } 108 |
110 switch(pkt->getSize()) { 111 case 1: 112 pkt->set<uint8_t>(data); 113 break; 114 case 2: 115 pkt->set<uint16_t>(data); 116 break; 117 case 4: 118 pkt->set<uint32_t>(data); 119 break; 120 default: 121 panic("KMI read size too big?\n"); 122 break; 123 } 124 | 109 pkt->setUintX(data, LittleEndianByteOrder); |
125 pkt->makeAtomicResponse(); 126 return pioDelay; 127} 128 129Tick 130Pl050::write(PacketPtr pkt) 131{ 132 133 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 134 135 Addr daddr = pkt->getAddr() - pioAddr; | 110 pkt->makeAtomicResponse(); 111 return pioDelay; 112} 113 114Tick 115Pl050::write(PacketPtr pkt) 116{ 117 118 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 119 120 Addr daddr = pkt->getAddr() - pioAddr; |
121 const uint32_t data = pkt->getUintX(LittleEndianByteOrder); |
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136 | 122 |
137 assert(pkt->getSize() == sizeof(uint8_t)); | 123 panic_if(pkt->getSize() != 1, 124 "PL050: Unexpected write size " 125 "(offset: %#x, data: %#x, size: %u)\n", 126 daddr, data, pkt->getSize()); |
138 | 127 |
139 | |
140 switch (daddr) { 141 case kmiCr: | 128 switch (daddr) { 129 case kmiCr: |
142 DPRINTF(Pl050, "Write Commmand: %#x\n", (uint32_t)pkt->get<uint8_t>()); 143 control = pkt->get<uint8_t>(); 144 updateIntStatus(); | 130 DPRINTF(Pl050, "Write Commmand: %#x\n", data); 131 // Use the update interrupts helper to make sure any interrupt 132 // mask changes are handled correctly. 133 setControl((uint8_t)data); |
145 break; 146 147 case kmiData: | 134 break; 135 136 case kmiData: |
148 DPRINTF(Pl050, "Write Data: %#x\n", (uint32_t)pkt->get<uint8_t>()); 149 ps2->hostWrite(pkt->get<uint8_t>()); 150 updateIntStatus(); | 137 DPRINTF(Pl050, "Write Data: %#x\n", data); 138 // Clear the TX interrupt before writing new data. 139 setTxInt(false); 140 ps2->hostWrite((uint8_t)data); 141 // Data is written in 0 time, so raise the TX interrupt again. 142 setTxInt(true); |
151 break; 152 153 case kmiClkDiv: | 143 break; 144 145 case kmiClkDiv: |
154 clkdiv = pkt->get<uint8_t>(); | 146 clkdiv = (uint8_t)data; |
155 break; 156 157 default: | 147 break; 148 149 default: |
158 warn("Tried to write PL050 at offset %#x that doesn't exist\n", daddr); | 150 warn("PL050: Unhandled write of %#x to offset %#x\n", data, daddr); |
159 break; 160 } 161 162 pkt->makeAtomicResponse(); 163 return pioDelay; 164} 165 | 151 break; 152 } 153 154 pkt->makeAtomicResponse(); 155 return pioDelay; 156} 157 |
158void 159Pl050::setTxInt(bool value) 160{ 161 InterruptReg ints = rawInterrupts; |
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166 | 162 |
163 ints.tx = value ? 1 : 0; 164 165 setInterrupts(ints); 166} 167 |
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167void | 168void |
168Pl050::updateIntStatus() | 169Pl050::updateRxInt() |
169{ | 170{ |
170 const bool old_interrupt(getInterrupt()); | 171 InterruptReg ints = rawInterrupts; |
171 | 172 |
172 rawInterrupts.rx = ps2->hostDataAvailable() ? 1 : 0; | 173 ints.rx = ps2->hostDataAvailable() ? 1 : 0; |
173 | 174 |
174 if ((!old_interrupt && getInterrupt()) && !intEvent.scheduled()) { 175 schedule(intEvent, curTick() + intDelay); 176 } else if (old_interrupt && !(getInterrupt())) { 177 gic->clearInt(intNum); | 175 setInterrupts(ints); 176} 177 178void 179Pl050::updateIntCtrl(InterruptReg ints, ControlReg ctrl) 180{ 181 const bool old_pending(getInterrupt()); 182 control = ctrl; 183 rawInterrupts = ints; 184 const bool new_pending(getInterrupt()); 185 186 if (!old_pending && new_pending) { 187 DPRINTF(Pl050, "Generate interrupt: rawInt=%#x ctrl=%#x int=%#x\n", 188 rawInterrupts, control, getInterrupt()); 189 gic->sendInt(intNum); 190 } else if (old_pending && !new_pending) { 191 DPRINTF(Pl050, "Clear interrupt: rawInt=%#x ctrl=%#x int=%#x\n", 192 rawInterrupts, control, getInterrupt()); 193 gic->clearInt(intNum); |
178 } 179} 180 181Pl050::InterruptReg 182Pl050::getInterrupt() const 183{ 184 InterruptReg tmp_interrupt(0); 185 186 tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable; 187 tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable; 188 189 return tmp_interrupt; 190} 191 192void | 194 } 195} 196 197Pl050::InterruptReg 198Pl050::getInterrupt() const 199{ 200 InterruptReg tmp_interrupt(0); 201 202 tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable; 203 tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable; 204 205 return tmp_interrupt; 206} 207 208void |
193Pl050::generateInterrupt() 194{ 195 DPRINTF(Pl050, "Generate Interrupt: rawInt=%#x ctrl=%#x int=%#x\n", 196 rawInterrupts, control, getInterrupt()); 197 198 if (getInterrupt()) { 199 gic->sendInt(intNum); 200 DPRINTF(Pl050, " -- Generated\n"); 201 } 202} 203 204void | |
205Pl050::serialize(CheckpointOut &cp) const 206{ | 209Pl050::serialize(CheckpointOut &cp) const 210{ |
207 uint8_t ctrlreg = control; 208 SERIALIZE_SCALAR(ctrlreg); 209 210 uint8_t stsreg = status; 211 SERIALIZE_SCALAR(stsreg); | 211 paramOut(cp, "ctrlreg", control); 212 paramOut(cp, "stsreg", status); |
212 SERIALIZE_SCALAR(clkdiv); | 213 SERIALIZE_SCALAR(clkdiv); |
213 214 uint8_t raw_ints = rawInterrupts; 215 SERIALIZE_SCALAR(raw_ints); | 214 paramOut(cp, "raw_ints", rawInterrupts); |
216} 217 218void 219Pl050::unserialize(CheckpointIn &cp) 220{ | 215} 216 217void 218Pl050::unserialize(CheckpointIn &cp) 219{ |
221 uint8_t ctrlreg; 222 UNSERIALIZE_SCALAR(ctrlreg); 223 control = ctrlreg; 224 225 uint8_t stsreg; 226 UNSERIALIZE_SCALAR(stsreg); 227 status = stsreg; 228 | 220 paramIn(cp, "ctrlreg", control); 221 paramIn(cp, "stsreg", status); |
229 UNSERIALIZE_SCALAR(clkdiv); | 222 UNSERIALIZE_SCALAR(clkdiv); |
230 231 uint8_t raw_ints; 232 UNSERIALIZE_SCALAR(raw_ints); 233 rawInterrupts = raw_ints; | 223 paramIn(cp, "raw_ints", rawInterrupts); |
234} 235 236Pl050 * 237Pl050Params::create() 238{ 239 return new Pl050(this); 240} | 224} 225 226Pl050 * 227Pl050Params::create() 228{ 229 return new Pl050(this); 230} |