kmi.cc (12659:3b44e9f66aac) kmi.cc (12660:c5caca5f7d68)
1/*
2 * Copyright (c) 2010, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * William Wang
42 */
43
44#include "dev/arm/kmi.hh"
45
46#include "base/trace.hh"
47#include "base/vnc/vncinput.hh"
48#include "debug/Pl050.hh"
49#include "dev/arm/amba_device.hh"
1/*
2 * Copyright (c) 2010, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * William Wang
42 */
43
44#include "dev/arm/kmi.hh"
45
46#include "base/trace.hh"
47#include "base/vnc/vncinput.hh"
48#include "debug/Pl050.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/ps2.hh"
51#include "dev/ps2/device.hh"
52#include "mem/packet.hh"
53#include "mem/packet_access.hh"
54
55Pl050::Pl050(const Pl050Params *p)
56 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0),
57 rawInterrupts(0),
58 intEvent([this]{ generateInterrupt(); }, name()),
59 ps2(p->ps2)
60{
61 ps2->hostRegDataAvailable([this]() { this->updateIntStatus(); });
62}
63
64Tick
65Pl050::read(PacketPtr pkt)
66{
67 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
68
69 Addr daddr = pkt->getAddr() - pioAddr;
70
71 uint32_t data = 0;
72
73 switch (daddr) {
74 case kmiCr:
75 DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control);
76 data = control;
77 break;
78
79 case kmiStat:
80 status.rxfull = ps2->hostDataAvailable() ? 1 : 0;
81 DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status);
82 data = status;
83 break;
84
85 case kmiData:
86 data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
87 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
88 updateIntStatus();
89 break;
90
91 case kmiClkDiv:
92 data = clkdiv;
93 break;
94
95 case kmiISR:
96 data = getInterrupt();
97 DPRINTF(Pl050, "Read Interrupts: %#x\n", getInterrupt());
98 break;
99
100 default:
101 if (readId(pkt, ambaId, pioAddr)) {
102 // Hack for variable size accesses
103 data = pkt->get<uint32_t>();
104 break;
105 }
106
107 warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr);
108 break;
109 }
110
111 switch(pkt->getSize()) {
112 case 1:
113 pkt->set<uint8_t>(data);
114 break;
115 case 2:
116 pkt->set<uint16_t>(data);
117 break;
118 case 4:
119 pkt->set<uint32_t>(data);
120 break;
121 default:
122 panic("KMI read size too big?\n");
123 break;
124 }
125
126 pkt->makeAtomicResponse();
127 return pioDelay;
128}
129
130Tick
131Pl050::write(PacketPtr pkt)
132{
133
134 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
135
136 Addr daddr = pkt->getAddr() - pioAddr;
137
138 assert(pkt->getSize() == sizeof(uint8_t));
139
140
141 switch (daddr) {
142 case kmiCr:
143 DPRINTF(Pl050, "Write Commmand: %#x\n", (uint32_t)pkt->get<uint8_t>());
144 control = pkt->get<uint8_t>();
145 updateIntStatus();
146 break;
147
148 case kmiData:
149 DPRINTF(Pl050, "Write Data: %#x\n", (uint32_t)pkt->get<uint8_t>());
150 ps2->hostWrite(pkt->get<uint8_t>());
151 updateIntStatus();
152 break;
153
154 case kmiClkDiv:
155 clkdiv = pkt->get<uint8_t>();
156 break;
157
158 default:
159 warn("Tried to write PL050 at offset %#x that doesn't exist\n", daddr);
160 break;
161 }
162
163 pkt->makeAtomicResponse();
164 return pioDelay;
165}
166
167
168void
169Pl050::updateIntStatus()
170{
171 const bool old_interrupt(getInterrupt());
172
173 rawInterrupts.rx = ps2->hostDataAvailable() ? 1 : 0;
174
175 if ((!old_interrupt && getInterrupt()) && !intEvent.scheduled()) {
176 schedule(intEvent, curTick() + intDelay);
177 } else if (old_interrupt && !(getInterrupt())) {
178 gic->clearInt(intNum);
179 }
180}
181
182Pl050::InterruptReg
183Pl050::getInterrupt() const
184{
185 InterruptReg tmp_interrupt(0);
186
187 tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable;
188 tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable;
189
190 return tmp_interrupt;
191}
192
193void
194Pl050::generateInterrupt()
195{
196 DPRINTF(Pl050, "Generate Interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
197 rawInterrupts, control, getInterrupt());
198
199 if (getInterrupt()) {
200 gic->sendInt(intNum);
201 DPRINTF(Pl050, " -- Generated\n");
202 }
203}
204
205void
206Pl050::serialize(CheckpointOut &cp) const
207{
208 uint8_t ctrlreg = control;
209 SERIALIZE_SCALAR(ctrlreg);
210
211 uint8_t stsreg = status;
212 SERIALIZE_SCALAR(stsreg);
213 SERIALIZE_SCALAR(clkdiv);
214
215 uint8_t raw_ints = rawInterrupts;
216 SERIALIZE_SCALAR(raw_ints);
217}
218
219void
220Pl050::unserialize(CheckpointIn &cp)
221{
222 uint8_t ctrlreg;
223 UNSERIALIZE_SCALAR(ctrlreg);
224 control = ctrlreg;
225
226 uint8_t stsreg;
227 UNSERIALIZE_SCALAR(stsreg);
228 status = stsreg;
229
230 UNSERIALIZE_SCALAR(clkdiv);
231
232 uint8_t raw_ints;
233 UNSERIALIZE_SCALAR(raw_ints);
234 rawInterrupts = raw_ints;
235}
236
237Pl050 *
238Pl050Params::create()
239{
240 return new Pl050(this);
241}
50#include "dev/ps2/device.hh"
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53
54Pl050::Pl050(const Pl050Params *p)
55 : AmbaIntDevice(p, 0xfff), control(0), status(0x43), clkdiv(0),
56 rawInterrupts(0),
57 intEvent([this]{ generateInterrupt(); }, name()),
58 ps2(p->ps2)
59{
60 ps2->hostRegDataAvailable([this]() { this->updateIntStatus(); });
61}
62
63Tick
64Pl050::read(PacketPtr pkt)
65{
66 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
67
68 Addr daddr = pkt->getAddr() - pioAddr;
69
70 uint32_t data = 0;
71
72 switch (daddr) {
73 case kmiCr:
74 DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control);
75 data = control;
76 break;
77
78 case kmiStat:
79 status.rxfull = ps2->hostDataAvailable() ? 1 : 0;
80 DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status);
81 data = status;
82 break;
83
84 case kmiData:
85 data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
86 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
87 updateIntStatus();
88 break;
89
90 case kmiClkDiv:
91 data = clkdiv;
92 break;
93
94 case kmiISR:
95 data = getInterrupt();
96 DPRINTF(Pl050, "Read Interrupts: %#x\n", getInterrupt());
97 break;
98
99 default:
100 if (readId(pkt, ambaId, pioAddr)) {
101 // Hack for variable size accesses
102 data = pkt->get<uint32_t>();
103 break;
104 }
105
106 warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr);
107 break;
108 }
109
110 switch(pkt->getSize()) {
111 case 1:
112 pkt->set<uint8_t>(data);
113 break;
114 case 2:
115 pkt->set<uint16_t>(data);
116 break;
117 case 4:
118 pkt->set<uint32_t>(data);
119 break;
120 default:
121 panic("KMI read size too big?\n");
122 break;
123 }
124
125 pkt->makeAtomicResponse();
126 return pioDelay;
127}
128
129Tick
130Pl050::write(PacketPtr pkt)
131{
132
133 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
134
135 Addr daddr = pkt->getAddr() - pioAddr;
136
137 assert(pkt->getSize() == sizeof(uint8_t));
138
139
140 switch (daddr) {
141 case kmiCr:
142 DPRINTF(Pl050, "Write Commmand: %#x\n", (uint32_t)pkt->get<uint8_t>());
143 control = pkt->get<uint8_t>();
144 updateIntStatus();
145 break;
146
147 case kmiData:
148 DPRINTF(Pl050, "Write Data: %#x\n", (uint32_t)pkt->get<uint8_t>());
149 ps2->hostWrite(pkt->get<uint8_t>());
150 updateIntStatus();
151 break;
152
153 case kmiClkDiv:
154 clkdiv = pkt->get<uint8_t>();
155 break;
156
157 default:
158 warn("Tried to write PL050 at offset %#x that doesn't exist\n", daddr);
159 break;
160 }
161
162 pkt->makeAtomicResponse();
163 return pioDelay;
164}
165
166
167void
168Pl050::updateIntStatus()
169{
170 const bool old_interrupt(getInterrupt());
171
172 rawInterrupts.rx = ps2->hostDataAvailable() ? 1 : 0;
173
174 if ((!old_interrupt && getInterrupt()) && !intEvent.scheduled()) {
175 schedule(intEvent, curTick() + intDelay);
176 } else if (old_interrupt && !(getInterrupt())) {
177 gic->clearInt(intNum);
178 }
179}
180
181Pl050::InterruptReg
182Pl050::getInterrupt() const
183{
184 InterruptReg tmp_interrupt(0);
185
186 tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable;
187 tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable;
188
189 return tmp_interrupt;
190}
191
192void
193Pl050::generateInterrupt()
194{
195 DPRINTF(Pl050, "Generate Interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
196 rawInterrupts, control, getInterrupt());
197
198 if (getInterrupt()) {
199 gic->sendInt(intNum);
200 DPRINTF(Pl050, " -- Generated\n");
201 }
202}
203
204void
205Pl050::serialize(CheckpointOut &cp) const
206{
207 uint8_t ctrlreg = control;
208 SERIALIZE_SCALAR(ctrlreg);
209
210 uint8_t stsreg = status;
211 SERIALIZE_SCALAR(stsreg);
212 SERIALIZE_SCALAR(clkdiv);
213
214 uint8_t raw_ints = rawInterrupts;
215 SERIALIZE_SCALAR(raw_ints);
216}
217
218void
219Pl050::unserialize(CheckpointIn &cp)
220{
221 uint8_t ctrlreg;
222 UNSERIALIZE_SCALAR(ctrlreg);
223 control = ctrlreg;
224
225 uint8_t stsreg;
226 UNSERIALIZE_SCALAR(stsreg);
227 status = stsreg;
228
229 UNSERIALIZE_SCALAR(clkdiv);
230
231 uint8_t raw_ints;
232 UNSERIALIZE_SCALAR(raw_ints);
233 rawInterrupts = raw_ints;
234}
235
236Pl050 *
237Pl050Params::create()
238{
239 return new Pl050(this);
240}