1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
44#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
45
46#include "base/addr_range.hh"
47#include "dev/arm/gic_v3.hh"
48#include "sim/serialize.hh"
49
50class Gicv3Distributor : public Serializable
51{
52 private:
53
54 friend class Gicv3Redistributor;
55 friend class Gicv3CPUInterface;
56 friend class Gicv3Its;
57
58 protected:
59
60 Gicv3 * gic;
61 const uint32_t itLines;
62
63 enum {
64 // Control Register
65 GICD_CTLR = 0x0000,
66 // Interrupt Controller Type Register
67 GICD_TYPER = 0x0004,
68 // Implementer Identification Register
69 GICD_IIDR = 0x0008,
70 // Error Reporting Status Register
71 GICD_STATUSR = 0x0010,
72 // Peripheral ID0 Register
73 GICD_PIDR0 = 0xffe0,
74 // Peripheral ID1 Register
75 GICD_PIDR1 = 0xffe4,
76 // Peripheral ID2 Register
77 GICD_PIDR2 = 0xffe8,
78 // Peripheral ID3 Register
79 GICD_PIDR3 = 0xffec,
80 // Peripheral ID4 Register
81 GICD_PIDR4 = 0xffd0,
82 // Peripheral ID5 Register
83 GICD_PIDR5 = 0xffd4,
84 // Peripheral ID6 Register
85 GICD_PIDR6 = 0xffd8,
86 // Peripheral ID7 Register
87 GICD_PIDR7 = 0xffdc,
88 };
89
90 // Interrupt Group Registers
91 static const AddrRange GICD_IGROUPR;
92 // Interrupt Set-Enable Registers
93 static const AddrRange GICD_ISENABLER;
94 // Interrupt Clear-Enable Registers
95 static const AddrRange GICD_ICENABLER;
96 // Interrupt Set-Pending Registers
97 static const AddrRange GICD_ISPENDR;
98 // Interrupt Clear-Pending Registers
99 static const AddrRange GICD_ICPENDR;
100 // Interrupt Set-Active Registers
101 static const AddrRange GICD_ISACTIVER;
102 // Interrupt Clear-Active Registers
103 static const AddrRange GICD_ICACTIVER;
104 // Interrupt Priority Registers
105 static const AddrRange GICD_IPRIORITYR;
106 // Interrupt Processor Targets Registers
107 static const AddrRange GICD_ITARGETSR; // GICv2 legacy
108 // Interrupt Configuration Registers
109 static const AddrRange GICD_ICFGR;
110 // Interrupt Group Modifier Registers
111 static const AddrRange GICD_IGRPMODR;
112 // Non-secure Access Control Registers
113 static const AddrRange GICD_NSACR;
114 // SGI Clear-Pending Registers
115 static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
116 // SGI Set-Pending Registers
117 static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
118 // Interrupt Routing Registers
119 static const AddrRange GICD_IROUTER;
120
121 BitUnion64(IROUTER)
122 Bitfield<63, 40> res0_1;
123 Bitfield<39, 32> Aff3;
124 Bitfield<31> IRM;
125 Bitfield<30, 24> res0_2;
126 Bitfield<23, 16> Aff2;
127 Bitfield<15, 8> Aff1;
128 Bitfield<7, 0> Aff0;
129 EndBitUnion(IROUTER)
130
131 static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
132 static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
133 static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
134 static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
135 static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
136 static const uint32_t GICD_CTLR_DS = 1 << 6;
137
138 bool ARE;
139 bool DS;
140 bool EnableGrp1S;
141 bool EnableGrp1NS;
142 bool EnableGrp0;
143 std::vector <uint8_t> irqGroup;
144 std::vector <bool> irqEnabled;
145 std::vector <bool> irqPending;
146 std::vector <bool> irqActive;
147 std::vector <uint8_t> irqPriority;
148 std::vector <Gicv3::IntTriggerType> irqConfig;
149 std::vector <uint8_t> irqGrpmod;
150 std::vector <uint8_t> irqNsacr;
151 std::vector <IROUTER> irqAffinityRouting;
152
153 uint32_t gicdPidr0;
154 uint32_t gicdPidr1;
155 uint32_t gicdPidr2;
156 uint32_t gicdPidr3;
157 uint32_t gicdPidr4;
158
159 public:
160
161 static const uint32_t ADDR_RANGE_SIZE = 0x10000;
162 static const uint32_t IDBITS = 0xf;
163
164 protected:
165
166 void activateIRQ(uint32_t int_id);
167 void deactivateIRQ(uint32_t int_id);
168 void fullUpdate();
169 Gicv3::GroupId getIntGroup(int int_id) const;
170
171 inline bool
172 groupEnabled(Gicv3::GroupId group) const
173 {
174 if (DS == 0) {
175 switch (group) {
176 case Gicv3::G0S:
177 return EnableGrp0;
178
179 case Gicv3::G1S:
180 return EnableGrp1S;
181
182 case Gicv3::G1NS:
183 return EnableGrp1NS;
184
185 default:
186 panic("Gicv3Distributor::groupEnabled(): "
187 "invalid group!\n");
188 }
189 } else {
190 switch (group) {
191 case Gicv3::G0S:
192 return EnableGrp0;
193
194 case Gicv3::G1S:
195 case Gicv3::G1NS:
196 return EnableGrp1NS;
197
198 default:
199 panic("Gicv3Distributor::groupEnabled(): "
200 "invalid group!\n");
201 }
202 }
203 }
204
205 Gicv3::IntStatus intStatus(uint32_t int_id) const;
206
207 inline bool isNotSPI(uint32_t int_id) const
208 {
209 if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) {
210 return true;
211 } else {
212 return false;
213 }
214 }
215
216 inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
217 {
218 return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
219 }
220
221 void reset();
222 void serialize(CheckpointOut & cp) const override;
223 void unserialize(CheckpointIn & cp) override;
224 void update();
| 1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
44#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
45
46#include "base/addr_range.hh"
47#include "dev/arm/gic_v3.hh"
48#include "sim/serialize.hh"
49
50class Gicv3Distributor : public Serializable
51{
52 private:
53
54 friend class Gicv3Redistributor;
55 friend class Gicv3CPUInterface;
56 friend class Gicv3Its;
57
58 protected:
59
60 Gicv3 * gic;
61 const uint32_t itLines;
62
63 enum {
64 // Control Register
65 GICD_CTLR = 0x0000,
66 // Interrupt Controller Type Register
67 GICD_TYPER = 0x0004,
68 // Implementer Identification Register
69 GICD_IIDR = 0x0008,
70 // Error Reporting Status Register
71 GICD_STATUSR = 0x0010,
72 // Peripheral ID0 Register
73 GICD_PIDR0 = 0xffe0,
74 // Peripheral ID1 Register
75 GICD_PIDR1 = 0xffe4,
76 // Peripheral ID2 Register
77 GICD_PIDR2 = 0xffe8,
78 // Peripheral ID3 Register
79 GICD_PIDR3 = 0xffec,
80 // Peripheral ID4 Register
81 GICD_PIDR4 = 0xffd0,
82 // Peripheral ID5 Register
83 GICD_PIDR5 = 0xffd4,
84 // Peripheral ID6 Register
85 GICD_PIDR6 = 0xffd8,
86 // Peripheral ID7 Register
87 GICD_PIDR7 = 0xffdc,
88 };
89
90 // Interrupt Group Registers
91 static const AddrRange GICD_IGROUPR;
92 // Interrupt Set-Enable Registers
93 static const AddrRange GICD_ISENABLER;
94 // Interrupt Clear-Enable Registers
95 static const AddrRange GICD_ICENABLER;
96 // Interrupt Set-Pending Registers
97 static const AddrRange GICD_ISPENDR;
98 // Interrupt Clear-Pending Registers
99 static const AddrRange GICD_ICPENDR;
100 // Interrupt Set-Active Registers
101 static const AddrRange GICD_ISACTIVER;
102 // Interrupt Clear-Active Registers
103 static const AddrRange GICD_ICACTIVER;
104 // Interrupt Priority Registers
105 static const AddrRange GICD_IPRIORITYR;
106 // Interrupt Processor Targets Registers
107 static const AddrRange GICD_ITARGETSR; // GICv2 legacy
108 // Interrupt Configuration Registers
109 static const AddrRange GICD_ICFGR;
110 // Interrupt Group Modifier Registers
111 static const AddrRange GICD_IGRPMODR;
112 // Non-secure Access Control Registers
113 static const AddrRange GICD_NSACR;
114 // SGI Clear-Pending Registers
115 static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
116 // SGI Set-Pending Registers
117 static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
118 // Interrupt Routing Registers
119 static const AddrRange GICD_IROUTER;
120
121 BitUnion64(IROUTER)
122 Bitfield<63, 40> res0_1;
123 Bitfield<39, 32> Aff3;
124 Bitfield<31> IRM;
125 Bitfield<30, 24> res0_2;
126 Bitfield<23, 16> Aff2;
127 Bitfield<15, 8> Aff1;
128 Bitfield<7, 0> Aff0;
129 EndBitUnion(IROUTER)
130
131 static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
132 static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
133 static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
134 static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
135 static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
136 static const uint32_t GICD_CTLR_DS = 1 << 6;
137
138 bool ARE;
139 bool DS;
140 bool EnableGrp1S;
141 bool EnableGrp1NS;
142 bool EnableGrp0;
143 std::vector <uint8_t> irqGroup;
144 std::vector <bool> irqEnabled;
145 std::vector <bool> irqPending;
146 std::vector <bool> irqActive;
147 std::vector <uint8_t> irqPriority;
148 std::vector <Gicv3::IntTriggerType> irqConfig;
149 std::vector <uint8_t> irqGrpmod;
150 std::vector <uint8_t> irqNsacr;
151 std::vector <IROUTER> irqAffinityRouting;
152
153 uint32_t gicdPidr0;
154 uint32_t gicdPidr1;
155 uint32_t gicdPidr2;
156 uint32_t gicdPidr3;
157 uint32_t gicdPidr4;
158
159 public:
160
161 static const uint32_t ADDR_RANGE_SIZE = 0x10000;
162 static const uint32_t IDBITS = 0xf;
163
164 protected:
165
166 void activateIRQ(uint32_t int_id);
167 void deactivateIRQ(uint32_t int_id);
168 void fullUpdate();
169 Gicv3::GroupId getIntGroup(int int_id) const;
170
171 inline bool
172 groupEnabled(Gicv3::GroupId group) const
173 {
174 if (DS == 0) {
175 switch (group) {
176 case Gicv3::G0S:
177 return EnableGrp0;
178
179 case Gicv3::G1S:
180 return EnableGrp1S;
181
182 case Gicv3::G1NS:
183 return EnableGrp1NS;
184
185 default:
186 panic("Gicv3Distributor::groupEnabled(): "
187 "invalid group!\n");
188 }
189 } else {
190 switch (group) {
191 case Gicv3::G0S:
192 return EnableGrp0;
193
194 case Gicv3::G1S:
195 case Gicv3::G1NS:
196 return EnableGrp1NS;
197
198 default:
199 panic("Gicv3Distributor::groupEnabled(): "
200 "invalid group!\n");
201 }
202 }
203 }
204
205 Gicv3::IntStatus intStatus(uint32_t int_id) const;
206
207 inline bool isNotSPI(uint32_t int_id) const
208 {
209 if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) {
210 return true;
211 } else {
212 return false;
213 }
214 }
215
216 inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
217 {
218 return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
219 }
220
221 void reset();
222 void serialize(CheckpointOut & cp) const override;
223 void unserialize(CheckpointIn & cp) override;
224 void update();
|
232 void init();
233 void initState();
234 uint64_t read(Addr addr, size_t size, bool is_secure_access);
235 void sendInt(uint32_t int_id);
236 void write(Addr addr, uint64_t data, size_t size,
237 bool is_secure_access);
238};
239
240#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
| 233 void init();
234 void initState();
235 uint64_t read(Addr addr, size_t size, bool is_secure_access);
236 void sendInt(uint32_t int_id);
237 void write(Addr addr, uint64_t data, size_t size,
238 bool is_secure_access);
239};
240
241#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
|