1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
32#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
33
34#include "base/addr_range.hh"
35#include "dev/arm/gic_v3.hh"
36#include "sim/serialize.hh"
37
38class Gicv3Distributor : public Serializable
39{
40 private:
41
42 friend class Gicv3Redistributor;
43 friend class Gicv3CPUInterface;
44
45 protected:
46
47 Gicv3 * gic;
48 const uint32_t itLines;
49
50 enum {
51 // Control Register
52 GICD_CTLR = 0x0000,
53 // Interrupt Controller Type Register
54 GICD_TYPER = 0x0004,
55 // Implementer Identification Register
56 GICD_IIDR = 0x0008,
57 // Error Reporting Status Register
58 GICD_STATUSR = 0x0010,
59 // Peripheral ID0 Register
60 GICD_PIDR0 = 0xffe0,
61 // Peripheral ID1 Register
62 GICD_PIDR1 = 0xffe4,
63 // Peripheral ID2 Register
64 GICD_PIDR2 = 0xffe8,
65 // Peripheral ID3 Register
66 GICD_PIDR3 = 0xffec,
67 // Peripheral ID4 Register
68 GICD_PIDR4 = 0xffd0,
69 // Peripheral ID5 Register
70 GICD_PIDR5 = 0xffd4,
71 // Peripheral ID6 Register
72 GICD_PIDR6 = 0xffd8,
73 // Peripheral ID7 Register
74 GICD_PIDR7 = 0xffdc,
75 };
76
77 // Interrupt Group Registers
78 static const AddrRange GICD_IGROUPR;
79 // Interrupt Set-Enable Registers
80 static const AddrRange GICD_ISENABLER;
81 // Interrupt Clear-Enable Registers
82 static const AddrRange GICD_ICENABLER;
83 // Interrupt Set-Pending Registers
84 static const AddrRange GICD_ISPENDR;
85 // Interrupt Clear-Pending Registers
86 static const AddrRange GICD_ICPENDR;
87 // Interrupt Set-Active Registers
88 static const AddrRange GICD_ISACTIVER;
89 // Interrupt Clear-Active Registers
90 static const AddrRange GICD_ICACTIVER;
91 // Interrupt Priority Registers
92 static const AddrRange GICD_IPRIORITYR;
93 // Interrupt Processor Targets Registers
94 static const AddrRange GICD_ITARGETSR; // GICv2 legacy
95 // Interrupt Configuration Registers
96 static const AddrRange GICD_ICFGR;
97 // Interrupt Group Modifier Registers
98 static const AddrRange GICD_IGRPMODR;
99 // Non-secure Access Control Registers
100 static const AddrRange GICD_NSACR;
101 // SGI Clear-Pending Registers
102 static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
103 // SGI Set-Pending Registers
104 static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
105 // Interrupt Routing Registers
106 static const AddrRange GICD_IROUTER;
107
108 BitUnion64(IROUTER)
109 Bitfield<63, 40> res0_1;
110 Bitfield<39, 32> Aff3;
111 Bitfield<31> IRM;
112 Bitfield<30, 24> res0_2;
113 Bitfield<23, 16> Aff2;
114 Bitfield<15, 8> Aff1;
115 Bitfield<7, 0> Aff0;
116 EndBitUnion(IROUTER)
117
118 static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
119 static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
120 static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
121 static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
122 static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
123 static const uint32_t GICD_CTLR_DS = 1 << 6;
124
125 bool ARE;
126 bool DS;
127 bool EnableGrp1S;
128 bool EnableGrp1NS;
129 bool EnableGrp0;
130 std::vector <uint8_t> irqGroup;
131 std::vector <bool> irqEnabled;
132 std::vector <bool> irqPending;
133 std::vector <bool> irqActive;
134 std::vector <uint8_t> irqPriority;
135 std::vector <Gicv3::IntTriggerType> irqConfig;
136 std::vector <uint8_t> irqGrpmod;
137 std::vector <uint8_t> irqNsacr;
138 std::vector <IROUTER> irqAffinityRouting;
139
140 public:
141
142 static const uint32_t ADDR_RANGE_SIZE = 0x10000;
143
144 protected:
145
146 void activateIRQ(uint32_t int_id);
147 void deactivateIRQ(uint32_t int_id);
148 void fullUpdate();
149 Gicv3::GroupId getIntGroup(int int_id) const;
150
151 inline bool
152 groupEnabled(Gicv3::GroupId group) const
153 {
154 if (DS == 0) {
155 switch (group) {
156 case Gicv3::G0S:
157 return EnableGrp0;
158
159 case Gicv3::G1S:
160 return EnableGrp1S;
161
162 case Gicv3::G1NS:
163 return EnableGrp1NS;
164
165 default:
166 panic("Gicv3Distributor::groupEnabled(): "
167 "invalid group!\n");
168 }
169 } else {
170 switch (group) {
171 case Gicv3::G0S:
172 return EnableGrp0;
173
174 case Gicv3::G1S:
175 case Gicv3::G1NS:
176 return EnableGrp1NS;
177
178 default:
179 panic("Gicv3Distributor::groupEnabled(): "
180 "invalid group!\n");
181 }
182 }
183 }
184
185 Gicv3::IntStatus intStatus(uint32_t int_id) const;
186
| 1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
32#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
33
34#include "base/addr_range.hh"
35#include "dev/arm/gic_v3.hh"
36#include "sim/serialize.hh"
37
38class Gicv3Distributor : public Serializable
39{
40 private:
41
42 friend class Gicv3Redistributor;
43 friend class Gicv3CPUInterface;
44
45 protected:
46
47 Gicv3 * gic;
48 const uint32_t itLines;
49
50 enum {
51 // Control Register
52 GICD_CTLR = 0x0000,
53 // Interrupt Controller Type Register
54 GICD_TYPER = 0x0004,
55 // Implementer Identification Register
56 GICD_IIDR = 0x0008,
57 // Error Reporting Status Register
58 GICD_STATUSR = 0x0010,
59 // Peripheral ID0 Register
60 GICD_PIDR0 = 0xffe0,
61 // Peripheral ID1 Register
62 GICD_PIDR1 = 0xffe4,
63 // Peripheral ID2 Register
64 GICD_PIDR2 = 0xffe8,
65 // Peripheral ID3 Register
66 GICD_PIDR3 = 0xffec,
67 // Peripheral ID4 Register
68 GICD_PIDR4 = 0xffd0,
69 // Peripheral ID5 Register
70 GICD_PIDR5 = 0xffd4,
71 // Peripheral ID6 Register
72 GICD_PIDR6 = 0xffd8,
73 // Peripheral ID7 Register
74 GICD_PIDR7 = 0xffdc,
75 };
76
77 // Interrupt Group Registers
78 static const AddrRange GICD_IGROUPR;
79 // Interrupt Set-Enable Registers
80 static const AddrRange GICD_ISENABLER;
81 // Interrupt Clear-Enable Registers
82 static const AddrRange GICD_ICENABLER;
83 // Interrupt Set-Pending Registers
84 static const AddrRange GICD_ISPENDR;
85 // Interrupt Clear-Pending Registers
86 static const AddrRange GICD_ICPENDR;
87 // Interrupt Set-Active Registers
88 static const AddrRange GICD_ISACTIVER;
89 // Interrupt Clear-Active Registers
90 static const AddrRange GICD_ICACTIVER;
91 // Interrupt Priority Registers
92 static const AddrRange GICD_IPRIORITYR;
93 // Interrupt Processor Targets Registers
94 static const AddrRange GICD_ITARGETSR; // GICv2 legacy
95 // Interrupt Configuration Registers
96 static const AddrRange GICD_ICFGR;
97 // Interrupt Group Modifier Registers
98 static const AddrRange GICD_IGRPMODR;
99 // Non-secure Access Control Registers
100 static const AddrRange GICD_NSACR;
101 // SGI Clear-Pending Registers
102 static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
103 // SGI Set-Pending Registers
104 static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
105 // Interrupt Routing Registers
106 static const AddrRange GICD_IROUTER;
107
108 BitUnion64(IROUTER)
109 Bitfield<63, 40> res0_1;
110 Bitfield<39, 32> Aff3;
111 Bitfield<31> IRM;
112 Bitfield<30, 24> res0_2;
113 Bitfield<23, 16> Aff2;
114 Bitfield<15, 8> Aff1;
115 Bitfield<7, 0> Aff0;
116 EndBitUnion(IROUTER)
117
118 static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
119 static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
120 static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
121 static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
122 static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
123 static const uint32_t GICD_CTLR_DS = 1 << 6;
124
125 bool ARE;
126 bool DS;
127 bool EnableGrp1S;
128 bool EnableGrp1NS;
129 bool EnableGrp0;
130 std::vector <uint8_t> irqGroup;
131 std::vector <bool> irqEnabled;
132 std::vector <bool> irqPending;
133 std::vector <bool> irqActive;
134 std::vector <uint8_t> irqPriority;
135 std::vector <Gicv3::IntTriggerType> irqConfig;
136 std::vector <uint8_t> irqGrpmod;
137 std::vector <uint8_t> irqNsacr;
138 std::vector <IROUTER> irqAffinityRouting;
139
140 public:
141
142 static const uint32_t ADDR_RANGE_SIZE = 0x10000;
143
144 protected:
145
146 void activateIRQ(uint32_t int_id);
147 void deactivateIRQ(uint32_t int_id);
148 void fullUpdate();
149 Gicv3::GroupId getIntGroup(int int_id) const;
150
151 inline bool
152 groupEnabled(Gicv3::GroupId group) const
153 {
154 if (DS == 0) {
155 switch (group) {
156 case Gicv3::G0S:
157 return EnableGrp0;
158
159 case Gicv3::G1S:
160 return EnableGrp1S;
161
162 case Gicv3::G1NS:
163 return EnableGrp1NS;
164
165 default:
166 panic("Gicv3Distributor::groupEnabled(): "
167 "invalid group!\n");
168 }
169 } else {
170 switch (group) {
171 case Gicv3::G0S:
172 return EnableGrp0;
173
174 case Gicv3::G1S:
175 case Gicv3::G1NS:
176 return EnableGrp1NS;
177
178 default:
179 panic("Gicv3Distributor::groupEnabled(): "
180 "invalid group!\n");
181 }
182 }
183 }
184
185 Gicv3::IntStatus intStatus(uint32_t int_id) const;
186
|
197 {
198 return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
199 }
200
201 void reset();
202 void serialize(CheckpointOut & cp) const override;
203 void unserialize(CheckpointIn & cp) override;
204 void update();
205 void updateAndInformCPUInterfaces();
206
207 public:
208
209 Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
210
211 void deassertSPI(uint32_t int_id);
212 void init();
213 void initState();
214 uint64_t read(Addr addr, size_t size, bool is_secure_access);
215 void sendInt(uint32_t int_id);
216 void write(Addr addr, uint64_t data, size_t size,
217 bool is_secure_access);
218};
219
220#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
| 197 {
198 return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
199 }
200
201 void reset();
202 void serialize(CheckpointOut & cp) const override;
203 void unserialize(CheckpointIn & cp) override;
204 void update();
205 void updateAndInformCPUInterfaces();
206
207 public:
208
209 Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
210
211 void deassertSPI(uint32_t int_id);
212 void init();
213 void initState();
214 uint64_t read(Addr addr, size_t size, bool is_secure_access);
215 void sendInt(uint32_t int_id);
216 void write(Addr addr, uint64_t data, size_t size,
217 bool is_secure_access);
218};
219
220#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
|