tsunami_pchip.cc (10905:a6ca6831e775) tsunami_pchip.cc (11244:a2af58a06c4e)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 */
31
32/** @file
33 * Tsunami PChip (pci)
34 */
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 */
31
32/** @file
33 * Tsunami PChip (pci)
34 */
35#include "dev/alpha/tsunami_pchip.hh"
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "config/the_isa.hh"
42#include "debug/Tsunami.hh"
43#include "dev/alpha/tsunami.hh"
36
37#include <deque>
38#include <string>
39#include <vector>
40
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "debug/Tsunami.hh"
44#include "dev/alpha/tsunami.hh"
44#include "dev/alpha/tsunami_pchip.hh"
45#include "dev/alpha/tsunami_cchip.hh"
45#include "dev/alpha/tsunamireg.h"
46#include "dev/alpha/tsunamireg.h"
47#include "dev/pcidev.hh"
46#include "mem/packet.hh"
47#include "mem/packet_access.hh"
48#include "sim/system.hh"
49
50using namespace std;
51//Should this be AlphaISA?
52using namespace TheISA;
53
54TsunamiPChip::TsunamiPChip(const Params *p)
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "sim/system.hh"
51
52using namespace std;
53//Should this be AlphaISA?
54using namespace TheISA;
55
56TsunamiPChip::TsunamiPChip(const Params *p)
55 : BasicPioDevice(p, 0x1000)
57 : GenericPciHost(p),
58 pioRange(RangeSize(p->pio_addr, 0x1000)),
59 pioDelay(p->pio_latency)
56{
57 for (int i = 0; i < 4; i++) {
58 wsba[i] = 0;
59 wsm[i] = 0;
60 tba[i] = 0;
61 }
62
63 // initialize pchip control register
64 pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
65
66 //Set back pointer in tsunami
67 p->tsunami->pchip = this;
68}
69
70Tick
71TsunamiPChip::read(PacketPtr pkt)
72{
60{
61 for (int i = 0; i < 4; i++) {
62 wsba[i] = 0;
63 wsm[i] = 0;
64 tba[i] = 0;
65 }
66
67 // initialize pchip control register
68 pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
69
70 //Set back pointer in tsunami
71 p->tsunami->pchip = this;
72}
73
74Tick
75TsunamiPChip::read(PacketPtr pkt)
76{
73 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
77 // We only need to handle our own configuration registers, pass
78 // unknown addresses to the generic code.
79 if (!pioRange.contains(pkt->getAddr()))
80 return GenericPciHost::read(pkt);
74
81
75 Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
82 Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;;
76 assert(pkt->getSize() == sizeof(uint64_t));
77
78
79 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
80
81 switch(daddr) {
82 case TSDEV_PC_WSBA0:
83 pkt->set(wsba[0]);

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137 break;
138 case TSDEV_PC_PMONCTL:
139 panic("PC_PMONCTL not implemented\n");
140 case TSDEV_PC_PMONCNT:
141 panic("PC_PMONCTN not implemented\n");
142 default:
143 panic("Default in PChip Read reached reading 0x%x\n", daddr);
144 }
83 assert(pkt->getSize() == sizeof(uint64_t));
84
85
86 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
87
88 switch(daddr) {
89 case TSDEV_PC_WSBA0:
90 pkt->set(wsba[0]);

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144 break;
145 case TSDEV_PC_PMONCTL:
146 panic("PC_PMONCTL not implemented\n");
147 case TSDEV_PC_PMONCNT:
148 panic("PC_PMONCTN not implemented\n");
149 default:
150 panic("Default in PChip Read reached reading 0x%x\n", daddr);
151 }
152
145 pkt->makeAtomicResponse();
146 return pioDelay;
147
148}
149
150Tick
151TsunamiPChip::write(PacketPtr pkt)
152{
153 pkt->makeAtomicResponse();
154 return pioDelay;
155
156}
157
158Tick
159TsunamiPChip::write(PacketPtr pkt)
160{
153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
154 Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
161 // We only need to handle our own configuration registers, pass
162 // unknown addresses to the generic code.
163 if (!pioRange.contains(pkt->getAddr()))
164 return GenericPciHost::write(pkt);
155
165
166 Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;
167
156 assert(pkt->getSize() == sizeof(uint64_t));
157
158 DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
159
160 switch(daddr) {
161 case TSDEV_PC_WSBA0:
162 wsba[0] = pkt->get<uint64_t>();
163 break;

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219 panic("Default in PChip write reached reading 0x%x\n", daddr);
220
221 } // uint64_t
222
223 pkt->makeAtomicResponse();
224 return pioDelay;
225}
226
168 assert(pkt->getSize() == sizeof(uint64_t));
169
170 DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
171
172 switch(daddr) {
173 case TSDEV_PC_WSBA0:
174 wsba[0] = pkt->get<uint64_t>();
175 break;

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231 panic("Default in PChip write reached reading 0x%x\n", daddr);
232
233 } // uint64_t
234
235 pkt->makeAtomicResponse();
236 return pioDelay;
237}
238
239
240AddrRangeList
241TsunamiPChip::getAddrRanges() const
242{
243 return AddrRangeList({
244 RangeSize(confBase, confSize),
245 pioRange
246 });
247}
248
249
227#define DMA_ADDR_MASK ULL(0x3ffffffff)
228
229Addr
250#define DMA_ADDR_MASK ULL(0x3ffffffff)
251
252Addr
230TsunamiPChip::translatePciToDma(Addr busAddr)
253TsunamiPChip::dmaAddr(const PciBusAddr &dev, Addr busAddr) const
231{
232 // compare the address to the window base registers
233 uint64_t tbaMask = 0;
234 uint64_t baMask = 0;
235
236 uint64_t windowMask = 0;
237 uint64_t windowBase = 0;
238

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296 }
297 }
298 }
299
300 // if no match was found, then return the original address
301 return busAddr;
302}
303
254{
255 // compare the address to the window base registers
256 uint64_t tbaMask = 0;
257 uint64_t baMask = 0;
258
259 uint64_t windowMask = 0;
260 uint64_t windowBase = 0;
261

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319 }
320 }
321 }
322
323 // if no match was found, then return the original address
324 return busAddr;
325}
326
304Addr
305TsunamiPChip::calcConfigAddr(int bus, int dev, int func)
306{
307 assert(func < 8);
308 assert(dev < 32);
309 assert(bus == 0);
310
311 return TsunamiPciBus0Config | (func << 8) | (dev << 11);
312}
313
314Addr
315TsunamiPChip::calcIOAddr(Addr addr)
316{
317 return TSUNAMI_PCI0_IO + addr;
318}
319
320Addr
321TsunamiPChip::calcMemAddr(Addr addr)
322{
323 return TSUNAMI_PCI0_MEMORY + addr;
324}
325
326void
327TsunamiPChip::serialize(CheckpointOut &cp) const
328{
329 SERIALIZE_SCALAR(pctl);
330 SERIALIZE_ARRAY(wsba, 4);
331 SERIALIZE_ARRAY(wsm, 4);
332 SERIALIZE_ARRAY(tba, 4);
333}

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328TsunamiPChip::serialize(CheckpointOut &cp) const
329{
330 SERIALIZE_SCALAR(pctl);
331 SERIALIZE_ARRAY(wsba, 4);
332 SERIALIZE_ARRAY(wsm, 4);
333 SERIALIZE_ARRAY(tba, 4);
334}

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