1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 */
31
32/** @file
33 * Tsunami PChip (pci)
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "dev/alpha/tsunami_pchip.hh"
42#include "dev/alpha/tsunamireg.h"
43#include "dev/alpha/tsunami.hh"
44#include "mem/packet.hh"
45#include "mem/packet_access.hh"
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 */
31
32/** @file
33 * Tsunami PChip (pci)
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "dev/alpha/tsunami_pchip.hh"
42#include "dev/alpha/tsunamireg.h"
43#include "dev/alpha/tsunami.hh"
44#include "mem/packet.hh"
45#include "mem/packet_access.hh"
|
46#include "sim/builder.hh"
| |
47#include "sim/system.hh"
48
49using namespace std;
50//Should this be AlphaISA?
51using namespace TheISA;
52
| 46#include "sim/system.hh"
47
48using namespace std;
49//Should this be AlphaISA?
50using namespace TheISA;
51
|
53TsunamiPChip::TsunamiPChip(Params *p)
| 52TsunamiPChip::TsunamiPChip(const Params *p)
|
54: BasicPioDevice(p)
55{
56 pioSize = 0x1000;
57
58 for (int i = 0; i < 4; i++) {
59 wsba[i] = 0;
60 wsm[i] = 0;
61 tba[i] = 0;
62 }
63
64 // initialize pchip control register
65 pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
66
67 //Set back pointer in tsunami
68 p->tsunami->pchip = this;
69}
70
71Tick
72TsunamiPChip::read(PacketPtr pkt)
73{
74 assert(pkt->result == Packet::Unknown);
75 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
76
77 pkt->allocate();
78 Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
79 assert(pkt->getSize() == sizeof(uint64_t));
80
81
82 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
83
84 switch(daddr) {
85 case TSDEV_PC_WSBA0:
86 pkt->set(wsba[0]);
87 break;
88 case TSDEV_PC_WSBA1:
89 pkt->set(wsba[1]);
90 break;
91 case TSDEV_PC_WSBA2:
92 pkt->set(wsba[2]);
93 break;
94 case TSDEV_PC_WSBA3:
95 pkt->set(wsba[3]);
96 break;
97 case TSDEV_PC_WSM0:
98 pkt->set(wsm[0]);
99 break;
100 case TSDEV_PC_WSM1:
101 pkt->set(wsm[1]);
102 break;
103 case TSDEV_PC_WSM2:
104 pkt->set(wsm[2]);
105 break;
106 case TSDEV_PC_WSM3:
107 pkt->set(wsm[3]);
108 break;
109 case TSDEV_PC_TBA0:
110 pkt->set(tba[0]);
111 break;
112 case TSDEV_PC_TBA1:
113 pkt->set(tba[1]);
114 break;
115 case TSDEV_PC_TBA2:
116 pkt->set(tba[2]);
117 break;
118 case TSDEV_PC_TBA3:
119 pkt->set(tba[3]);
120 break;
121 case TSDEV_PC_PCTL:
122 pkt->set(pctl);
123 break;
124 case TSDEV_PC_PLAT:
125 panic("PC_PLAT not implemented\n");
126 case TSDEV_PC_RES:
127 panic("PC_RES not implemented\n");
128 case TSDEV_PC_PERROR:
129 pkt->set((uint64_t)0x00);
130 break;
131 case TSDEV_PC_PERRMASK:
132 pkt->set((uint64_t)0x00);
133 break;
134 case TSDEV_PC_PERRSET:
135 panic("PC_PERRSET not implemented\n");
136 case TSDEV_PC_TLBIV:
137 panic("PC_TLBIV not implemented\n");
138 case TSDEV_PC_TLBIA:
139 pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
140 break;
141 case TSDEV_PC_PMONCTL:
142 panic("PC_PMONCTL not implemented\n");
143 case TSDEV_PC_PMONCNT:
144 panic("PC_PMONCTN not implemented\n");
145 default:
146 panic("Default in PChip Read reached reading 0x%x\n", daddr);
147 }
148 pkt->result = Packet::Success;
149 return pioDelay;
150
151}
152
153Tick
154TsunamiPChip::write(PacketPtr pkt)
155{
156 assert(pkt->result == Packet::Unknown);
157 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
158 Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
159
160 assert(pkt->getSize() == sizeof(uint64_t));
161
162 DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
163
164 switch(daddr) {
165 case TSDEV_PC_WSBA0:
166 wsba[0] = pkt->get<uint64_t>();
167 break;
168 case TSDEV_PC_WSBA1:
169 wsba[1] = pkt->get<uint64_t>();
170 break;
171 case TSDEV_PC_WSBA2:
172 wsba[2] = pkt->get<uint64_t>();
173 break;
174 case TSDEV_PC_WSBA3:
175 wsba[3] = pkt->get<uint64_t>();
176 break;
177 case TSDEV_PC_WSM0:
178 wsm[0] = pkt->get<uint64_t>();
179 break;
180 case TSDEV_PC_WSM1:
181 wsm[1] = pkt->get<uint64_t>();
182 break;
183 case TSDEV_PC_WSM2:
184 wsm[2] = pkt->get<uint64_t>();
185 break;
186 case TSDEV_PC_WSM3:
187 wsm[3] = pkt->get<uint64_t>();
188 break;
189 case TSDEV_PC_TBA0:
190 tba[0] = pkt->get<uint64_t>();
191 break;
192 case TSDEV_PC_TBA1:
193 tba[1] = pkt->get<uint64_t>();
194 break;
195 case TSDEV_PC_TBA2:
196 tba[2] = pkt->get<uint64_t>();
197 break;
198 case TSDEV_PC_TBA3:
199 tba[3] = pkt->get<uint64_t>();
200 break;
201 case TSDEV_PC_PCTL:
202 pctl = pkt->get<uint64_t>();
203 break;
204 case TSDEV_PC_PLAT:
205 panic("PC_PLAT not implemented\n");
206 case TSDEV_PC_RES:
207 panic("PC_RES not implemented\n");
208 case TSDEV_PC_PERROR:
209 break;
210 case TSDEV_PC_PERRMASK:
211 panic("PC_PERRMASK not implemented\n");
212 case TSDEV_PC_PERRSET:
213 panic("PC_PERRSET not implemented\n");
214 case TSDEV_PC_TLBIV:
215 panic("PC_TLBIV not implemented\n");
216 case TSDEV_PC_TLBIA:
217 break; // value ignored, supposted to invalidate SG TLB
218 case TSDEV_PC_PMONCTL:
219 panic("PC_PMONCTL not implemented\n");
220 case TSDEV_PC_PMONCNT:
221 panic("PC_PMONCTN not implemented\n");
222 default:
223 panic("Default in PChip write reached reading 0x%x\n", daddr);
224
225 } // uint64_t
226
227 pkt->result = Packet::Success;
228 return pioDelay;
229}
230
231#define DMA_ADDR_MASK ULL(0x3ffffffff)
232
233Addr
234TsunamiPChip::translatePciToDma(Addr busAddr)
235{
236 // compare the address to the window base registers
237 uint64_t tbaMask = 0;
238 uint64_t baMask = 0;
239
240 uint64_t windowMask = 0;
241 uint64_t windowBase = 0;
242
243 uint64_t pteEntry = 0;
244
245 Addr pteAddr;
246 Addr dmaAddr;
247
248#if 0
249 DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
250 for (int i = 0; i < 4; i++) {
251 DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
252 i, wsba[i], wsm[i]);
253
254 windowBase = wsba[i];
255 windowMask = ~wsm[i] & (ULL(0xfff) << 20);
256
257 if ((busAddr & windowMask) == (windowBase & windowMask)) {
258 DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
259 i, windowBase, windowMask, (busAddr & windowMask),
260 (windowBase & windowMask));
261 }
262 }
263#endif
264
265 for (int i = 0; i < 4; i++) {
266
267 windowBase = wsba[i];
268 windowMask = ~wsm[i] & (ULL(0xfff) << 20);
269
270 if ((busAddr & windowMask) == (windowBase & windowMask)) {
271
272 if (wsba[i] & 0x1) { // see if enabled
273 if (wsba[i] & 0x2) { // see if SG bit is set
274 /** @todo
275 This currently is faked by just doing a direct
276 read from memory, however, to be realistic, this
277 needs to actually do a bus transaction. The process
278 is explained in the tsunami documentation on page
279 10-12 and basically munges the address to look up a
280 PTE from a table in memory and then uses that mapping
281 to create an address for the SG page
282 */
283
284 tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
285 baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
286 pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
287
288 pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
289
290 dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
291
292 } else {
293 baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
294 tbaMask = ~baMask;
295 dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
296 }
297
298 return (dmaAddr & DMA_ADDR_MASK);
299 }
300 }
301 }
302
303 // if no match was found, then return the original address
304 return busAddr;
305}
306Addr
307TsunamiPChip::calcConfigAddr(int bus, int dev, int func)
308{
309 assert(func < 8);
310 assert(dev < 32);
311 assert(bus == 0);
312
313 return TsunamiPciBus0Config | (func << 8) | (dev << 11);
314}
315
316
317
318void
319TsunamiPChip::serialize(std::ostream &os)
320{
321 SERIALIZE_SCALAR(pctl);
322 SERIALIZE_ARRAY(wsba, 4);
323 SERIALIZE_ARRAY(wsm, 4);
324 SERIALIZE_ARRAY(tba, 4);
325}
326
327void
328TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
329{
330 UNSERIALIZE_SCALAR(pctl);
331 UNSERIALIZE_ARRAY(wsba, 4);
332 UNSERIALIZE_ARRAY(wsm, 4);
333 UNSERIALIZE_ARRAY(tba, 4);
334}
335
336
| 53: BasicPioDevice(p)
54{
55 pioSize = 0x1000;
56
57 for (int i = 0; i < 4; i++) {
58 wsba[i] = 0;
59 wsm[i] = 0;
60 tba[i] = 0;
61 }
62
63 // initialize pchip control register
64 pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
65
66 //Set back pointer in tsunami
67 p->tsunami->pchip = this;
68}
69
70Tick
71TsunamiPChip::read(PacketPtr pkt)
72{
73 assert(pkt->result == Packet::Unknown);
74 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
75
76 pkt->allocate();
77 Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
78 assert(pkt->getSize() == sizeof(uint64_t));
79
80
81 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
82
83 switch(daddr) {
84 case TSDEV_PC_WSBA0:
85 pkt->set(wsba[0]);
86 break;
87 case TSDEV_PC_WSBA1:
88 pkt->set(wsba[1]);
89 break;
90 case TSDEV_PC_WSBA2:
91 pkt->set(wsba[2]);
92 break;
93 case TSDEV_PC_WSBA3:
94 pkt->set(wsba[3]);
95 break;
96 case TSDEV_PC_WSM0:
97 pkt->set(wsm[0]);
98 break;
99 case TSDEV_PC_WSM1:
100 pkt->set(wsm[1]);
101 break;
102 case TSDEV_PC_WSM2:
103 pkt->set(wsm[2]);
104 break;
105 case TSDEV_PC_WSM3:
106 pkt->set(wsm[3]);
107 break;
108 case TSDEV_PC_TBA0:
109 pkt->set(tba[0]);
110 break;
111 case TSDEV_PC_TBA1:
112 pkt->set(tba[1]);
113 break;
114 case TSDEV_PC_TBA2:
115 pkt->set(tba[2]);
116 break;
117 case TSDEV_PC_TBA3:
118 pkt->set(tba[3]);
119 break;
120 case TSDEV_PC_PCTL:
121 pkt->set(pctl);
122 break;
123 case TSDEV_PC_PLAT:
124 panic("PC_PLAT not implemented\n");
125 case TSDEV_PC_RES:
126 panic("PC_RES not implemented\n");
127 case TSDEV_PC_PERROR:
128 pkt->set((uint64_t)0x00);
129 break;
130 case TSDEV_PC_PERRMASK:
131 pkt->set((uint64_t)0x00);
132 break;
133 case TSDEV_PC_PERRSET:
134 panic("PC_PERRSET not implemented\n");
135 case TSDEV_PC_TLBIV:
136 panic("PC_TLBIV not implemented\n");
137 case TSDEV_PC_TLBIA:
138 pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
139 break;
140 case TSDEV_PC_PMONCTL:
141 panic("PC_PMONCTL not implemented\n");
142 case TSDEV_PC_PMONCNT:
143 panic("PC_PMONCTN not implemented\n");
144 default:
145 panic("Default in PChip Read reached reading 0x%x\n", daddr);
146 }
147 pkt->result = Packet::Success;
148 return pioDelay;
149
150}
151
152Tick
153TsunamiPChip::write(PacketPtr pkt)
154{
155 assert(pkt->result == Packet::Unknown);
156 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
157 Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
158
159 assert(pkt->getSize() == sizeof(uint64_t));
160
161 DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
162
163 switch(daddr) {
164 case TSDEV_PC_WSBA0:
165 wsba[0] = pkt->get<uint64_t>();
166 break;
167 case TSDEV_PC_WSBA1:
168 wsba[1] = pkt->get<uint64_t>();
169 break;
170 case TSDEV_PC_WSBA2:
171 wsba[2] = pkt->get<uint64_t>();
172 break;
173 case TSDEV_PC_WSBA3:
174 wsba[3] = pkt->get<uint64_t>();
175 break;
176 case TSDEV_PC_WSM0:
177 wsm[0] = pkt->get<uint64_t>();
178 break;
179 case TSDEV_PC_WSM1:
180 wsm[1] = pkt->get<uint64_t>();
181 break;
182 case TSDEV_PC_WSM2:
183 wsm[2] = pkt->get<uint64_t>();
184 break;
185 case TSDEV_PC_WSM3:
186 wsm[3] = pkt->get<uint64_t>();
187 break;
188 case TSDEV_PC_TBA0:
189 tba[0] = pkt->get<uint64_t>();
190 break;
191 case TSDEV_PC_TBA1:
192 tba[1] = pkt->get<uint64_t>();
193 break;
194 case TSDEV_PC_TBA2:
195 tba[2] = pkt->get<uint64_t>();
196 break;
197 case TSDEV_PC_TBA3:
198 tba[3] = pkt->get<uint64_t>();
199 break;
200 case TSDEV_PC_PCTL:
201 pctl = pkt->get<uint64_t>();
202 break;
203 case TSDEV_PC_PLAT:
204 panic("PC_PLAT not implemented\n");
205 case TSDEV_PC_RES:
206 panic("PC_RES not implemented\n");
207 case TSDEV_PC_PERROR:
208 break;
209 case TSDEV_PC_PERRMASK:
210 panic("PC_PERRMASK not implemented\n");
211 case TSDEV_PC_PERRSET:
212 panic("PC_PERRSET not implemented\n");
213 case TSDEV_PC_TLBIV:
214 panic("PC_TLBIV not implemented\n");
215 case TSDEV_PC_TLBIA:
216 break; // value ignored, supposted to invalidate SG TLB
217 case TSDEV_PC_PMONCTL:
218 panic("PC_PMONCTL not implemented\n");
219 case TSDEV_PC_PMONCNT:
220 panic("PC_PMONCTN not implemented\n");
221 default:
222 panic("Default in PChip write reached reading 0x%x\n", daddr);
223
224 } // uint64_t
225
226 pkt->result = Packet::Success;
227 return pioDelay;
228}
229
230#define DMA_ADDR_MASK ULL(0x3ffffffff)
231
232Addr
233TsunamiPChip::translatePciToDma(Addr busAddr)
234{
235 // compare the address to the window base registers
236 uint64_t tbaMask = 0;
237 uint64_t baMask = 0;
238
239 uint64_t windowMask = 0;
240 uint64_t windowBase = 0;
241
242 uint64_t pteEntry = 0;
243
244 Addr pteAddr;
245 Addr dmaAddr;
246
247#if 0
248 DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
249 for (int i = 0; i < 4; i++) {
250 DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
251 i, wsba[i], wsm[i]);
252
253 windowBase = wsba[i];
254 windowMask = ~wsm[i] & (ULL(0xfff) << 20);
255
256 if ((busAddr & windowMask) == (windowBase & windowMask)) {
257 DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
258 i, windowBase, windowMask, (busAddr & windowMask),
259 (windowBase & windowMask));
260 }
261 }
262#endif
263
264 for (int i = 0; i < 4; i++) {
265
266 windowBase = wsba[i];
267 windowMask = ~wsm[i] & (ULL(0xfff) << 20);
268
269 if ((busAddr & windowMask) == (windowBase & windowMask)) {
270
271 if (wsba[i] & 0x1) { // see if enabled
272 if (wsba[i] & 0x2) { // see if SG bit is set
273 /** @todo
274 This currently is faked by just doing a direct
275 read from memory, however, to be realistic, this
276 needs to actually do a bus transaction. The process
277 is explained in the tsunami documentation on page
278 10-12 and basically munges the address to look up a
279 PTE from a table in memory and then uses that mapping
280 to create an address for the SG page
281 */
282
283 tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
284 baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
285 pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
286
287 pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
288
289 dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
290
291 } else {
292 baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
293 tbaMask = ~baMask;
294 dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
295 }
296
297 return (dmaAddr & DMA_ADDR_MASK);
298 }
299 }
300 }
301
302 // if no match was found, then return the original address
303 return busAddr;
304}
305Addr
306TsunamiPChip::calcConfigAddr(int bus, int dev, int func)
307{
308 assert(func < 8);
309 assert(dev < 32);
310 assert(bus == 0);
311
312 return TsunamiPciBus0Config | (func << 8) | (dev << 11);
313}
314
315
316
317void
318TsunamiPChip::serialize(std::ostream &os)
319{
320 SERIALIZE_SCALAR(pctl);
321 SERIALIZE_ARRAY(wsba, 4);
322 SERIALIZE_ARRAY(wsm, 4);
323 SERIALIZE_ARRAY(tba, 4);
324}
325
326void
327TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
328{
329 UNSERIALIZE_SCALAR(pctl);
330 UNSERIALIZE_ARRAY(wsba, 4);
331 UNSERIALIZE_ARRAY(wsm, 4);
332 UNSERIALIZE_ARRAY(tba, 4);
333}
334
335
|
337BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
338
339 Param<Addr> pio_addr;
340 Param<Tick> pio_latency;
341 SimObjectParam<Platform *> platform;
342 SimObjectParam<System *> system;
343 SimObjectParam<Tsunami *> tsunami;
344
345END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
346
347BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
348
349 INIT_PARAM(pio_addr, "Device Address"),
350 INIT_PARAM(pio_latency, "Programmed IO latency"),
351 INIT_PARAM(platform, "platform"),
352 INIT_PARAM(system, "system object"),
353 INIT_PARAM(tsunami, "Tsunami")
354
355END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
356
357CREATE_SIM_OBJECT(TsunamiPChip)
| 336TsunamiPChip *
337TsunamiPChipParams::create()
|
358{
| 338{
|
359 TsunamiPChip::Params *p = new TsunamiPChip::Params;
360 p->name = getInstanceName();
361 p->pio_addr = pio_addr;
362 p->pio_delay = pio_latency;
363 p->platform = platform;
364 p->system = system;
365 p->tsunami = tsunami;
366 return new TsunamiPChip(p);
| 339 return new TsunamiPChip(this);
|
367}
| 340}
|
368
369REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
| |
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