tsunami_io.hh (5443:394d180e8c04) tsunami_io.hh (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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51 */
52class TsunamiIO : public BasicPioDevice
53{
54 private:
55 struct tm tm;
56
57 protected:
58
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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51 */
52class TsunamiIO : public BasicPioDevice
53{
54 private:
55 struct tm tm;
56
57 protected:
58
59 class TsunamiRTC : public MC146818
59 class RTC : public MC146818
60 {
61 public:
60 {
61 public:
62 Tsunami * tsunami;
63 TsunamiRTC(const std::string &n, const TsunamiIOParams *p);
62 Tsunami *tsunami;
63 RTC(const std::string &n, const TsunamiIOParams *p);
64
65 protected:
66 void handleEvent()
67 {
68 //Actually interrupt the processor here
69 tsunami->cchip->postRTC();
70 }
71 };

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89 bool picInterrupting;
90
91 /** A pointer to the Tsunami device which be belong to */
92 Tsunami *tsunami;
93
94 /** Intel 8253 Periodic Interval Timer */
95 Intel8254Timer pitimer;
96
64
65 protected:
66 void handleEvent()
67 {
68 //Actually interrupt the processor here
69 tsunami->cchip->postRTC();
70 }
71 };

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89 bool picInterrupting;
90
91 /** A pointer to the Tsunami device which be belong to */
92 Tsunami *tsunami;
93
94 /** Intel 8253 Periodic Interval Timer */
95 Intel8254Timer pitimer;
96
97 TsunamiRTC rtc;
97 RTC rtc;
98
99 uint8_t rtcAddr;
100
101 /** The interval is set via two writes to the PIT.
102 * This variable contains a flag as to how many writes have happened, and
103 * the time so far.
104 */
105 uint16_t timerData;

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99 uint8_t rtcAddr;
100
101 /** The interval is set via two writes to the PIT.
102 * This variable contains a flag as to how many writes have happened, and
103 * the time so far.
104 */
105 uint16_t timerData;

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