tsunami_io.hh (5336:c7e21f4e5a2e) tsunami_io.hh (5392:c3a45fac35f8)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34 * Tsunami I/O Space mapping including RTC/timer interrupts
35 */
36
37#ifndef __DEV_TSUNAMI_IO_HH__
38#define __DEV_TSUNAMI_IO_HH__
39
40#include "base/range.hh"
41#include "dev/alpha/tsunami.hh"
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34 * Tsunami I/O Space mapping including RTC/timer interrupts
35 */
36
37#ifndef __DEV_TSUNAMI_IO_HH__
38#define __DEV_TSUNAMI_IO_HH__
39
40#include "base/range.hh"
41#include "dev/alpha/tsunami.hh"
42#include "dev/mc146818.hh"
42#include "dev/io_device.hh"
43#include "params/TsunamiIO.hh"
44#include "sim/eventq.hh"
45
46/**
47 * Tsunami I/O device is a catch all for all the south bridge stuff we care
48 * to implement.
49 */
50class TsunamiIO : public BasicPioDevice
51{
52 private:
53 struct tm tm;
54
55 protected:
43#include "dev/io_device.hh"
44#include "params/TsunamiIO.hh"
45#include "sim/eventq.hh"
46
47/**
48 * Tsunami I/O device is a catch all for all the south bridge stuff we care
49 * to implement.
50 */
51class TsunamiIO : public BasicPioDevice
52{
53 private:
54 struct tm tm;
55
56 protected:
56 /** Real-Time Clock (MC146818) */
57 class RTC
58 {
59 private:
60 /** Event for RTC periodic interrupt */
61 struct RTCEvent : public Event
62 {
63 /** A pointer back to tsunami to create interrupt the processor. */
64 Tsunami* tsunami;
65 Tick interval;
66
57
67 RTCEvent(Tsunami* t, Tick i);
68
69 /** Schedule the RTC periodic interrupt */
70 void scheduleIntr();
71
72 /** Event process to occur at interrupt*/
73 virtual void process();
74
75 /** Event description */
76 virtual const char *description() const;
77 };
78
79 private:
80 std::string _name;
81 const std::string &name() const { return _name; }
82
83 /** RTC periodic interrupt event */
84 RTCEvent event;
85
86 /** Current RTC register address/index */
87 int addr;
88
89 /** Data for real-time clock function */
90 union {
91 uint8_t clock_data[10];
92
93 struct {
94 uint8_t sec;
95 uint8_t sec_alrm;
96 uint8_t min;
97 uint8_t min_alrm;
98 uint8_t hour;
99 uint8_t hour_alrm;
100 uint8_t wday;
101 uint8_t mday;
102 uint8_t mon;
103 uint8_t year;
104 };
105 };
106
107 /** RTC status register A */
108 uint8_t stat_regA;
109
110 /** RTC status register B */
111 uint8_t stat_regB;
112
58 class TsunamiRTC : public MC146818
59 {
113 public:
60 public:
114 RTC(const std::string &name, Tsunami* tsunami,
115 const TsunamiIOParams *params);
61 Tsunami * tsunami;
62 TsunamiRTC(const std::string &n, const TsunamiIOParams *p);
116
63
117 /** RTC address port: write address of RTC RAM data to access */
118 void writeAddr(const uint8_t data);
119
120 /** RTC write data */
121 void writeData(const uint8_t data);
122
123 /** RTC read data */
124 uint8_t readData();
125
126 /**
127 * Serialize this object to the given output stream.
128 * @param base The base name of the counter object.
129 * @param os The stream to serialize to.
130 */
131 void serialize(const std::string &base, std::ostream &os);
132
133 /**
134 * Reconstruct the state of this object from a checkpoint.
135 * @param base The base name of the counter object.
136 * @param cp The checkpoint use.
137 * @param section The section name of this object
138 */
139 void unserialize(const std::string &base, Checkpoint *cp,
140 const std::string &section);
64 protected:
65 void handleEvent()
66 {
67 //Actually interrupt the processor here
68 tsunami->cchip->postRTC();
69 }
141 };
142
143 /** Programmable Interval Timer (Intel 8254) */
144 class PITimer
145 {
146 /** Counter element for PIT */
147 class Counter
148 {

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291 bool picInterrupting;
292
293 /** A pointer to the Tsunami device which be belong to */
294 Tsunami *tsunami;
295
296 /** Intel 8253 Periodic Interval Timer */
297 PITimer pitimer;
298
70 };
71
72 /** Programmable Interval Timer (Intel 8254) */
73 class PITimer
74 {
75 /** Counter element for PIT */
76 class Counter
77 {

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220 bool picInterrupting;
221
222 /** A pointer to the Tsunami device which be belong to */
223 Tsunami *tsunami;
224
225 /** Intel 8253 Periodic Interval Timer */
226 PITimer pitimer;
227
299 RTC rtc;
228 TsunamiRTC rtc;
300
229
230 uint8_t rtcAddr;
231
301 /** The interval is set via two writes to the PIT.
302 * This variable contains a flag as to how many writes have happened, and
303 * the time so far.
304 */
305 uint16_t timerData;
306
307 public:
308 /**

--- 50 unchanged lines hidden --- 		232 /** The interval is set via two writes to the PIT.
233 * This variable contains a flag as to how many writes have happened, and
234 * the time so far.
235 */
236 uint16_t timerData;
237
238 public:
239 /**

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