1/* 2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 138 unchanged lines hidden (view full) --- 147 bool read(TraceElement& element); 148 }; 149 150 public: 151 152 /** 153 * Create a trace generator. 154 * |
155 * @param obj SimObject owning this sequence generator 156 * @param master_id MasterID related to the memory requests |
157 * @param _duration duration of this state before transitioning 158 * @param trace_file File to read the transactions from 159 * @param addr_offset Positive offset to add to trace address 160 */ |
161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration, |
162 const std::string& trace_file, Addr addr_offset) |
163 : BaseGen(obj, master_id, _duration), |
164 trace(trace_file), 165 tickOffset(0), 166 addrOffset(addr_offset), 167 traceComplete(false) 168 { 169 } 170 171 void enter(); --- 42 unchanged lines hidden --- |