| BaseTrafficGen.py (13665:9c7fe3811b88) | BaseTrafficGen.py (13892:0182a0601f66) |
|---|---|
| 1# Copyright (c) 2012, 2016, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 25 unchanged lines hidden (view full) --- 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Thomas Grass 37# Andreas Hansson 38# Sascha Bischoff 39 40from m5.params import * 41from m5.proxy import * | 1# Copyright (c) 2012, 2016, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 25 unchanged lines hidden (view full) --- 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Thomas Grass 37# Andreas Hansson 38# Sascha Bischoff 39 40from m5.params import * 41from m5.proxy import * |
| 42from m5.objects.MemObject import MemObject | 42from m5.objects.ClockedObject import ClockedObject |
| 43 44# Types of Stream Generators. 45# Those are orthogonal to the other generators in the TrafficGen 46# and are meant to initialize the stream and substream IDs for 47# every memory request, regardless of how the packet has been 48# generated (Random, Linear, Trace etc) 49class StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ] 50 51# The traffic generator is a master module that generates stimuli for 52# the memory system, based on a collection of simple behaviours that 53# are either probabilistic or based on traces. It can be used stand 54# alone for creating test cases for interconnect and memory 55# controllers, or function as a black-box replacement for system 56# components that are not yet modelled in detail, e.g. a video engine 57# or baseband subsystem in an SoC. | 43 44# Types of Stream Generators. 45# Those are orthogonal to the other generators in the TrafficGen 46# and are meant to initialize the stream and substream IDs for 47# every memory request, regardless of how the packet has been 48# generated (Random, Linear, Trace etc) 49class StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ] 50 51# The traffic generator is a master module that generates stimuli for 52# the memory system, based on a collection of simple behaviours that 53# are either probabilistic or based on traces. It can be used stand 54# alone for creating test cases for interconnect and memory 55# controllers, or function as a black-box replacement for system 56# components that are not yet modelled in detail, e.g. a video engine 57# or baseband subsystem in an SoC. |
| 58class BaseTrafficGen(MemObject): | 58class BaseTrafficGen(ClockedObject): |
| 59 type = 'BaseTrafficGen' 60 abstract = True 61 cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" 62 63 # Port used for sending requests and receiving responses 64 port = MasterPort("Master port") 65 66 # System used to determine the mode of the memory system --- 21 unchanged lines hidden --- | 59 type = 'BaseTrafficGen' 60 abstract = True 61 cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" 62 63 # Port used for sending requests and receiving responses 64 port = MasterPort("Master port") 65 66 # System used to determine the mode of the memory system --- 21 unchanged lines hidden --- |