1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/directedtest/RubyDirectedTester.hh"
43
44#include "base/trace.hh"
45#include "cpu/testers/directedtest/DirectedGenerator.hh"
46#include "debug/DirectedTest.hh"
47#include "sim/sim_exit.hh"
48
49RubyDirectedTester::RubyDirectedTester(const Params *p)
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/directedtest/RubyDirectedTester.hh"
43
44#include "base/trace.hh"
45#include "cpu/testers/directedtest/DirectedGenerator.hh"
46#include "debug/DirectedTest.hh"
47#include "sim/sim_exit.hh"
48
49RubyDirectedTester::RubyDirectedTester(const Params *p)
|
50 : MemObject(p), directedStartEvent(this),
| 50 : MemObject(p),
51 directedStartEvent([this]{ wakeup(); }, "Directed tick",
52 false, Event::CPU_Tick_Pri),
|
51 m_requests_to_complete(p->requests_to_complete),
52 generator(p->generator)
53{
54 m_requests_completed = 0;
55
56 // create the ports
57 for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
58 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
59 this, i));
60 }
61
62 // add the check start event to the event queue
63 schedule(directedStartEvent, 1);
64}
65
66RubyDirectedTester::~RubyDirectedTester()
67{
68 for (int i = 0; i < ports.size(); i++)
69 delete ports[i];
70}
71
72void
73RubyDirectedTester::init()
74{
75 assert(ports.size() > 0);
76 generator->setDirectedTester(this);
77}
78
79BaseMasterPort &
80RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
81{
82 if (if_name != "cpuPort") {
83 // pass it along to our super class
84 return MemObject::getMasterPort(if_name, idx);
85 } else {
86 if (idx >= static_cast<int>(ports.size())) {
87 panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
88 }
89
90 return *ports[idx];
91 }
92}
93
94bool
95RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
96{
97 tester->hitCallback(id, pkt->getAddr());
98
99 //
100 // Now that the tester has completed, delete the packet, then return
101 //
102 delete pkt->req;
103 delete pkt;
104 return true;
105}
106
107MasterPort*
108RubyDirectedTester::getCpuPort(int idx)
109{
110 assert(idx >= 0 && idx < ports.size());
111
112 return ports[idx];
113}
114
115void
116RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
117{
118 DPRINTF(DirectedTest,
119 "completed request for proc: %d addr: 0x%x\n",
120 proc,
121 addr);
122
123 generator->performCallback(proc, addr);
124 schedule(directedStartEvent, curTick());
125}
126
127void
128RubyDirectedTester::wakeup()
129{
130 if (m_requests_completed < m_requests_to_complete) {
131 if (!generator->initiate()) {
132 schedule(directedStartEvent, curTick() + 1);
133 }
134 } else {
135 exitSimLoop("Ruby DirectedTester completed");
136 }
137}
138
139RubyDirectedTester *
140RubyDirectedTesterParams::create()
141{
142 return new RubyDirectedTester(this);
143}
| 53 m_requests_to_complete(p->requests_to_complete),
54 generator(p->generator)
55{
56 m_requests_completed = 0;
57
58 // create the ports
59 for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
60 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
61 this, i));
62 }
63
64 // add the check start event to the event queue
65 schedule(directedStartEvent, 1);
66}
67
68RubyDirectedTester::~RubyDirectedTester()
69{
70 for (int i = 0; i < ports.size(); i++)
71 delete ports[i];
72}
73
74void
75RubyDirectedTester::init()
76{
77 assert(ports.size() > 0);
78 generator->setDirectedTester(this);
79}
80
81BaseMasterPort &
82RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
83{
84 if (if_name != "cpuPort") {
85 // pass it along to our super class
86 return MemObject::getMasterPort(if_name, idx);
87 } else {
88 if (idx >= static_cast<int>(ports.size())) {
89 panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
90 }
91
92 return *ports[idx];
93 }
94}
95
96bool
97RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
98{
99 tester->hitCallback(id, pkt->getAddr());
100
101 //
102 // Now that the tester has completed, delete the packet, then return
103 //
104 delete pkt->req;
105 delete pkt;
106 return true;
107}
108
109MasterPort*
110RubyDirectedTester::getCpuPort(int idx)
111{
112 assert(idx >= 0 && idx < ports.size());
113
114 return ports[idx];
115}
116
117void
118RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
119{
120 DPRINTF(DirectedTest,
121 "completed request for proc: %d addr: 0x%x\n",
122 proc,
123 addr);
124
125 generator->performCallback(proc, addr);
126 schedule(directedStartEvent, curTick());
127}
128
129void
130RubyDirectedTester::wakeup()
131{
132 if (m_requests_completed < m_requests_to_complete) {
133 if (!generator->initiate()) {
134 schedule(directedStartEvent, curTick() + 1);
135 }
136 } else {
137 exitSimLoop("Ruby DirectedTester completed");
138 }
139}
140
141RubyDirectedTester *
142RubyDirectedTesterParams::create()
143{
144 return new RubyDirectedTester(this);
145}
|