1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
|
42#include "cpu/testers/directedtest/DirectedGenerator.hh"
| |
43#include "cpu/testers/directedtest/RubyDirectedTester.hh"
| 42#include "cpu/testers/directedtest/RubyDirectedTester.hh"
|
| 43
44#include "cpu/testers/directedtest/DirectedGenerator.hh"
|
44#include "debug/DirectedTest.hh"
45#include "sim/sim_exit.hh"
46
47RubyDirectedTester::RubyDirectedTester(const Params *p)
48 : MemObject(p), directedStartEvent(this),
49 m_requests_to_complete(p->requests_to_complete),
50 generator(p->generator)
51{
52 m_requests_completed = 0;
53
54 // create the ports
55 for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
56 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
57 this, i));
58 }
59
60 // add the check start event to the event queue
61 schedule(directedStartEvent, 1);
62}
63
64RubyDirectedTester::~RubyDirectedTester()
65{
66 for (int i = 0; i < ports.size(); i++)
67 delete ports[i];
68}
69
70void
71RubyDirectedTester::init()
72{
73 assert(ports.size() > 0);
74 generator->setDirectedTester(this);
75}
76
77BaseMasterPort &
78RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
79{
80 if (if_name != "cpuPort") {
81 // pass it along to our super class
82 return MemObject::getMasterPort(if_name, idx);
83 } else {
84 if (idx >= static_cast<int>(ports.size())) {
85 panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
86 }
87
88 return *ports[idx];
89 }
90}
91
92bool
93RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
94{
95 tester->hitCallback(id, pkt->getAddr());
96
97 //
98 // Now that the tester has completed, delete the packet, then return
99 //
100 delete pkt->req;
101 delete pkt;
102 return true;
103}
104
105MasterPort*
106RubyDirectedTester::getCpuPort(int idx)
107{
108 assert(idx >= 0 && idx < ports.size());
109
110 return ports[idx];
111}
112
113void
114RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
115{
116 DPRINTF(DirectedTest,
117 "completed request for proc: %d addr: 0x%x\n",
118 proc,
119 addr);
120
121 generator->performCallback(proc, addr);
122 schedule(directedStartEvent, curTick());
123}
124
125void
126RubyDirectedTester::wakeup()
127{
128 if (m_requests_completed < m_requests_to_complete) {
129 if (!generator->initiate()) {
130 schedule(directedStartEvent, curTick() + 1);
131 }
132 } else {
133 exitSimLoop("Ruby DirectedTester completed");
134 }
135}
136
137RubyDirectedTester *
138RubyDirectedTesterParams::create()
139{
140 return new RubyDirectedTester(this);
141}
| 45#include "debug/DirectedTest.hh"
46#include "sim/sim_exit.hh"
47
48RubyDirectedTester::RubyDirectedTester(const Params *p)
49 : MemObject(p), directedStartEvent(this),
50 m_requests_to_complete(p->requests_to_complete),
51 generator(p->generator)
52{
53 m_requests_completed = 0;
54
55 // create the ports
56 for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
57 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
58 this, i));
59 }
60
61 // add the check start event to the event queue
62 schedule(directedStartEvent, 1);
63}
64
65RubyDirectedTester::~RubyDirectedTester()
66{
67 for (int i = 0; i < ports.size(); i++)
68 delete ports[i];
69}
70
71void
72RubyDirectedTester::init()
73{
74 assert(ports.size() > 0);
75 generator->setDirectedTester(this);
76}
77
78BaseMasterPort &
79RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
80{
81 if (if_name != "cpuPort") {
82 // pass it along to our super class
83 return MemObject::getMasterPort(if_name, idx);
84 } else {
85 if (idx >= static_cast<int>(ports.size())) {
86 panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
87 }
88
89 return *ports[idx];
90 }
91}
92
93bool
94RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
95{
96 tester->hitCallback(id, pkt->getAddr());
97
98 //
99 // Now that the tester has completed, delete the packet, then return
100 //
101 delete pkt->req;
102 delete pkt;
103 return true;
104}
105
106MasterPort*
107RubyDirectedTester::getCpuPort(int idx)
108{
109 assert(idx >= 0 && idx < ports.size());
110
111 return ports[idx];
112}
113
114void
115RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
116{
117 DPRINTF(DirectedTest,
118 "completed request for proc: %d addr: 0x%x\n",
119 proc,
120 addr);
121
122 generator->performCallback(proc, addr);
123 schedule(directedStartEvent, curTick());
124}
125
126void
127RubyDirectedTester::wakeup()
128{
129 if (m_requests_completed < m_requests_to_complete) {
130 if (!generator->initiate()) {
131 schedule(directedStartEvent, curTick() + 1);
132 }
133 } else {
134 exitSimLoop("Ruby DirectedTester completed");
135 }
136}
137
138RubyDirectedTester *
139RubyDirectedTesterParams::create()
140{
141 return new RubyDirectedTester(this);
142}
|