1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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31Import('*')
32
33need_simple_base = False
34if 'AtomicSimpleCPU' in env['CPU_MODELS']:
35 need_simple_base = True
36 SimObject('AtomicSimpleCPU.py')
37 Source('atomic.cc')
38
39 # The NonCachingSimpleCPU is really an atomic CPU in
40 # disguise. It's therefore always enabled when the atomic CPU is
41 # enabled.
42 SimObject('NonCachingSimpleCPU.py')
43 Source('noncaching.cc')
44
45if 'TimingSimpleCPU' in env['CPU_MODELS']:
46 need_simple_base = True
47 SimObject('TimingSimpleCPU.py')
48 Source('timing.cc')
49
50if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
51 'TimingSimpleCPU' in env['CPU_MODELS']:
52 DebugFlag('SimpleCPU')
53
54if need_simple_base:
55 Source('base.cc')
56 SimObject('BaseSimpleCPU.py')